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(Updated Nov. 20, 2014, 6:27 a.m.) Review request for Default. Changes ------- Addressed raised issues. Repository: gem5 Description (updated) ------- Changeset 10553:d4148bafebad --------------------------- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. Diffs (updated) ----- src/arch/alpha/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/arm/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/mips/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/power/tlb.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/sparc/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table_impl.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/Process.py 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 Diff: http://reviews.gem5.org/r/2462/diff/ Testing ------- Quick regressions testing done. Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
