changeset de2979ff873a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=de2979ff873a
description:
stats: Bump stats for o3 LSQ changes
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
1594 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt |
14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt |
14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt |
5016 +++++-----
4 files changed, 3319 insertions(+), 3319 deletions(-)
diffs (truncated from 6860 to 300 lines):
diff -r a8d612fa170b -r de2979ff873a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Dec 02 06:08:03 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Dec 02 06:08:05 2014 -0500
@@ -4,20 +4,20 @@
sim_ticks 1905067807000 #
Number of ticks simulated
final_tick 1905067807000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 163944 #
Simulator instruction rate (inst/s)
-host_op_rate 163944 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5458738398 #
Simulator tick rate (ticks/s)
-host_mem_usage 318552 #
Number of bytes of host memory used
-host_seconds 348.99 #
Real time elapsed on the host
+host_inst_rate 154638 #
Simulator instruction rate (inst/s)
+host_op_rate 154638 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5148903745 #
Simulator tick rate (ticks/s)
+host_mem_usage 378896 #
Number of bytes of host memory used
+host_seconds 369.99 #
Real time elapsed on the host
sim_insts 57215334 #
Number of instructions simulated
sim_ops 57215334 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
system.clk_domain.clock 1000 #
Clock period in ticks
system.physmem.bytes_read::cpu0.inst 865344 #
Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24709248 #
Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 960 #
Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 118912 #
Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 545600 #
Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 960 #
Number of bytes read from this memory
system.physmem.bytes_read::total 26240064 #
Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 865344 #
Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 118912 #
Number of instructions bytes read from this memory
@@ -27,18 +27,18 @@
system.physmem.bytes_written::total 7817024 #
Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13521 #
Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 386082 #
Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 15 #
Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1858 #
Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 8525 #
Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 15 #
Number of read requests responded to by this memory
system.physmem.num_reads::total 410001 #
Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 80589 #
Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 #
Number of write requests responded to by this memory
system.physmem.num_writes::total 122141 #
Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 454233 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12970272 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 504 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 62419 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 286394 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 504 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13773822 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 454233 #
Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 62419 #
Instruction read bandwidth from this memory (bytes/s)
@@ -49,9 +49,9 @@
system.physmem.bw_total::writebacks 2707356 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 454233 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12970272 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1396427 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 62419 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 286394 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1396427 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17877100 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 410001 #
Number of read requests accepted
system.physmem.writeReqs 122141 #
Number of write requests accepted
@@ -317,467 +317,6 @@
system.physmem.totalEnergy::1 1276845922050 #
Total energy per rank (pJ)
system.physmem.averagePower::0 670.232898 #
Core power per rank (mW)
system.physmem.averagePower::1 670.238474 #
Core power per rank (mW)
-system.membus.trans_dist::ReadReq 296853 #
Transaction distribution
-system.membus.trans_dist::ReadResp 296773 #
Transaction distribution
-system.membus.trans_dist::WriteReq 13665 #
Transaction distribution
-system.membus.trans_dist::WriteResp 13665 #
Transaction distribution
-system.membus.trans_dist::Writeback 80589 #
Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 41552
# Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 41552
# Transaction distribution
-system.membus.trans_dist::UpgradeReq 14563 #
Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 9639 #
Transaction distribution
-system.membus.trans_dist::UpgradeResp 6364 #
Transaction distribution
-system.membus.trans_dist::ReadExReq 121274 #
Transaction distribution
-system.membus.trans_dist::ReadExResp 120582 #
Transaction distribution
-system.membus.trans_dist::BadAddressError 80 #
Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714
# Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819
# Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio
160 # Packet count per connected master and
slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 973693
# Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port
83296 # Packet count per connected master and slave
(bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 83296
# Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1056989 #
Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682
# Cumulative packet size per connected master and slave
(bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800
# Cumulative packet size per connected master and slave
(bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 31475482
# Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port
2660288 # Cumulative packet size per connected master and
slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2660288
# Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 34135770 #
Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 18692 #
Total snoops (count)
-system.membus.snoop_fanout::samples 557285 #
Request fanout histogram
-system.membus.snoop_fanout::mean 1 #
Request fanout histogram
-system.membus.snoop_fanout::stdev 0 #
Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% #
Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% #
Request fanout histogram
-system.membus.snoop_fanout::1 557285 100.00% 100.00% #
Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% #
Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% #
Request fanout histogram
-system.membus.snoop_fanout::min_value 1 #
Request fanout histogram
-system.membus.snoop_fanout::max_value 1 #
Request fanout histogram
-system.membus.snoop_fanout::total 557285 #
Request fanout histogram
-system.membus.reqLayer0.occupancy 40450499 #
Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 #
Layer utilization (%)
-system.membus.reqLayer1.occupancy 1545398747 #
Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.1 #
Layer utilization (%)
-system.membus.reqLayer2.occupancy 102000 #
Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 #
Layer utilization (%)
-system.membus.respLayer1.occupancy 3825672402 #
Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 #
Layer utilization (%)
-system.membus.respLayer2.occupancy 43153245 #
Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 #
Layer utilization (%)
-system.cpu_clk_domain.clock 500 #
Clock period in ticks
-system.l2c.tags.replacements 344236 #
number of replacements
-system.l2c.tags.tagsinuse 65255.823465 #
Cycle average of tags in use
-system.l2c.tags.total_refs 2587778 #
Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 409374 #
Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.321305 #
Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 7093665750 #
Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 53392.763161 #
Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5322.213179 #
Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6227.888257 #
Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 220.740542 #
Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 92.218326 #
Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.814709 #
Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.081211 #
Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.095030 #
Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.003368 #
Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.001407 #
Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.995725 #
Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 65138 #
Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 230
# Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 3694
# Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 4797
# Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4255
# Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52162
# Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.993927 #
Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 27098951 #
Number of tag accesses
-system.l2c.tags.data_accesses 27098951 #
Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 802459 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 696077 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 311437 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 94339 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1904312 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 804733 #
number of Writeback hits
-system.l2c.Writeback_hits::total 804733 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 166 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 431 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 597 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 52 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 26 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 78 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 138280 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 34809 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 173089 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 802459 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 834357 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 311437 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 129148 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2077401 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 802459 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 834357 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 311437 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 129148 #
number of overall hits
-system.l2c.overall_hits::total 2077401 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13534 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 273199 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1862 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 907 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 289502 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2870 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1562 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 4432 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 736 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 745 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1481 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 113374 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 7659 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 121033 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13534 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 386573 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1862 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 8566 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 410535 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13534 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 386573 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1862 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 8566 #
number of overall misses
-system.l2c.overall_misses::total 410535 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 1040639500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 17951579250
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 147621500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 80108498
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 19219948748 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 1096455
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 8459610
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 9556065 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1292445
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 1455438
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 9386780343
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 797590458
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 10184370801 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 1040639500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 27338359593 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 147621500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 877698956 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 29404319549 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 1040639500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 27338359593
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 147621500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 877698956
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 29404319549 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 815993 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 969276 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 313299 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 95246 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2193814 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 804733 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 804733 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 3036 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1993 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 5029 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 788
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 771
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1559 #
number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 251654 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 42468 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 294122 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 815993 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1220930 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 313299 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 137714 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2487936 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 815993 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1220930 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 313299 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 137714 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2487936 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.016586 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.281859 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.005943 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.009523 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.131963 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945323
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783743
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.881289 #
miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934010
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.966278
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.949968 #
miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.450515 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.180348 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.411506 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.016586 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.316622 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.005943 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.062201 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.165010 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.016586 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.316622 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.005943 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.062201 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.165010 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76890.756613
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65708.802924
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79281.149302
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 88322.489526
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 66389.692465
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.040070
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5415.883483
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2156.151850
# average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1756.039402
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.782550
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 982.740041
# average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82794.823707
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 104137.675676
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 84145.404980
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76890.756613
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70719.785378
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 79281.149302
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 102463.104833
# average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71624.391462 #
average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76890.756613
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70719.785378
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 79281.149302
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 102463.104833
# average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71624.391462
# average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 #
number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.l2c.blocked::no_targets 0 #
number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan #
average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan #
average number of cycles each access was blocked
-system.l2c.fast_writes 0 #
number of fast writes performed
-system.l2c.cache_copies 0 #
number of cache copies performed
-system.l2c.writebacks::writebacks 80589 #
number of writebacks
-system.l2c.writebacks::total 80589 #
number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 13 #
number of ReadReq MSHR hits
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