----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2566/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 10610:b2007283d4e0 --------------------------- arm: Raise an alignment fault if a PC has illegal alignment We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. Diffs ----- src/arch/arm/SConscript 8fc6e7a835d1 src/arch/arm/decoder.cc 8fc6e7a835d1 src/arch/arm/insts/pseudo.hh PRE-CREATION src/arch/arm/insts/pseudo.cc PRE-CREATION src/arch/arm/isa/bitfields.isa 8fc6e7a835d1 src/arch/arm/isa/decoder/decoder.isa 8fc6e7a835d1 src/arch/arm/isa/formats/formats.isa 8fc6e7a835d1 src/arch/arm/isa/formats/pseudo.isa PRE-CREATION src/arch/arm/isa/includes.isa 8fc6e7a835d1 src/arch/arm/tlb.cc 8fc6e7a835d1 src/arch/arm/types.hh 8fc6e7a835d1 Diff: http://reviews.gem5.org/r/2566/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
