changeset c5a2c5ef6e68 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c5a2c5ef6e68
description:
minor: fixed LSQ MasterPortID
Minor was reporting the data cache access as ".inst" accesses.
This just switches the MasterPortID to dataMasterPortId.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/cpu/minor/lsq.cc | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r ae3b12c845b8 -r c5a2c5ef6e68 src/cpu/minor/lsq.cc
--- a/src/cpu/minor/lsq.cc Sat Jan 03 17:51:48 2015 -0600
+++ b/src/cpu/minor/lsq.cc Sat Jan 03 17:51:48 2015 -0600
@@ -1503,7 +1503,7 @@
request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0);
request->request.setVirt(0 /* asid */,
- addr, size, flags, cpu.instMasterId(),
+ addr, size, flags, cpu.dataMasterId(),
/* I've no idea why we need the PC, but give it */
inst->pc.instAddr());
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