changeset e9bc4cde5d8e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e9bc4cde5d8e
description:
cpuid, x86: Revert "Enabling more features in CPUid"
That change enables CPUID bits for features that aren't implemented in
gem5.
If a simulated system tries to use those features because it was told it
could, bad things can happen.
diffstat:
src/arch/x86/cpuid.cc | 18 ++----------------
1 files changed, 2 insertions(+), 16 deletions(-)
diffs (37 lines):
diff -r 9ac724889705 -r e9bc4cde5d8e src/arch/x86/cpuid.cc
--- a/src/arch/x86/cpuid.cc Sun Jan 04 13:02:12 2015 -0600
+++ b/src/arch/x86/cpuid.cc Tue Jan 06 22:13:56 2015 -0800
@@ -96,15 +96,8 @@
stringToRegister(vendorString + 8));
break;
case FamilyModelSteppingBrandFeatures:
- /** Features Enabling
- * rdx, enabling most of the features except:
- * FXSR, FFXSR, Page1GB in EDX
- *
- * rcx, disabling most of the features except:
- * SSE4A, XOP, FMA4 in ECX
- */
result = CpuidResult(0x00020f51, 0x00000405,
- 0xe3d3fbff, 0x00010840);
+ 0xe3d3fbff, 0x00000001);
break;
case NameString1:
case NameString2:
@@ -160,15 +153,8 @@
stringToRegister(vendorString + 8));
break;
case FamilyModelStepping:
- /** Features Enabling
- * rdx, enabling most of the features except:
- * HTT in EDX
- *
- * rcx, disabling most of the features except:
- * SSE3, SSSE3, FMA, SSE41, XSAVE, AVX in ECX
- */
result = CpuidResult(0x00020f51, 0x00000805,
- 0xe7dbfbff, 0x14081201);
+ 0xe7dbfbff, 0x00000001);
break;
default:
warn("x86 cpuid: unimplemented function %u", funcNum);
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
