changeset e3fc6bc7f97e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e3fc6bc7f97e
description:
mem: Clean up Request initialisation
This patch tidies up how we create and set the fields of a Request. In
essence it tries to use the constructor where possible (as opposed to
setPhys and setVirt), thus avoiding spreading the information across a
number of locations. In fact, setPhys is made private as part of this
patch, and a number of places where we callede setVirt instead uses
the appropriate constructor.
diffstat:
src/arch/arm/isa.cc | 12 +--
src/cpu/checker/cpu.cc | 8 +-
src/cpu/kvm/base.cc | 5 +-
src/cpu/kvm/base.hh | 3 -
src/cpu/kvm/x86_cpu.cc | 5 +-
src/cpu/kvm/x86_cpu.hh | 3 -
src/cpu/simple/timing.cc | 16 ++---
src/cpu/simple/timing.hh | 2 +-
src/cpu/testers/memtest/memtest.cc | 6 +-
src/cpu/testers/networktest/networktest.cc | 12 ++--
src/mem/port_proxy.cc | 8 +--
src/mem/request.hh | 82 ++++++++++++++---------------
src/mem/ruby/system/CacheRecorder.cc | 8 +-
13 files changed, 76 insertions(+), 94 deletions(-)
diffs (truncated from 469 to 300 lines):
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/arch/arm/isa.cc Thu Jan 22 05:00:53 2015 -0500
@@ -1490,7 +1490,6 @@
case MISCREG_ATS1HR:
case MISCREG_ATS1HW:
{
- RequestPtr req = new Request;
unsigned flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
@@ -1562,16 +1561,16 @@
// can't be an atomic translation because that causes problems
// with unexpected atomic snoop requests.
warn("Translating via MISCREG(%d) in functional mode! Fix
Me!\n", misc_reg);
- req->setVirt(0, val, 1, flags, Request::funcMasterId,
- tc->pcState().pc());
- req->setThreadContext(tc->contextId(), tc->threadId());
- fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
tranType);
+ Request req(0, val, 1, flags, Request::funcMasterId,
+ tc->pcState().pc(), tc->contextId(),
+ tc->threadId());
+ fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode,
tranType);
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
MiscReg newVal;
if (fault == NoFault) {
- Addr paddr = req->getPaddr();
+ Addr paddr = req.getPaddr();
if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
newVal = (paddr & mask(39, 12)) |
@@ -1605,7 +1604,6 @@
"MISCREG: Translated addr 0x%08x fault fsr %#x: PAR:
0x%08x\n",
val, fsr, newVal);
}
- delete req;
setMiscRegNoEffect(MISCREG_PAR, newVal);
return;
}
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/checker/cpu.cc Thu Jan 22 05:00:53 2015 -0500
@@ -154,8 +154,8 @@
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
- memReq = new Request();
- memReq->setVirt(0, addr, size, flags, masterId,
thread->pcState().instAddr());
+ memReq = new Request(0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId(), 0);
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
@@ -242,8 +242,8 @@
// Need to account for a multiple access like Atomic and Timing CPUs
while (1) {
- memReq = new Request();
- memReq->setVirt(0, addr, size, flags, masterId,
thread->pcState().instAddr());
+ memReq = new Request(0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId(), 0);
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/kvm/base.cc
--- a/src/cpu/kvm/base.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/kvm/base.cc Thu Jan 22 05:00:53 2015 -0500
@@ -118,8 +118,6 @@
// initialize CPU, including PC
if (FullSystem && !switchedOut())
TheISA::initCPU(tc, tc->contextId());
-
- mmio_req.setThreadContext(tc->contextId(), 0);
}
void
@@ -995,7 +993,8 @@
ThreadContext *tc(thread->getTC());
syncThreadContext();
- mmio_req.setPhys(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ mmio_req.setThreadContext(tc->contextId(), 0);
// Some architectures do need to massage physical addresses a bit
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/kvm/base.hh
--- a/src/cpu/kvm/base.hh Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/kvm/base.hh Thu Jan 22 05:00:53 2015 -0500
@@ -574,9 +574,6 @@
/** Unused dummy port for the instruction interface */
KVMCpuPort instPort;
- /** Pre-allocated MMIO memory request */
- Request mmio_req;
-
/**
* Is the gem5 context dirty? Set to true to force an update of
* the KVM vCPU state upon the next call to kvmRun().
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/kvm/x86_cpu.cc
--- a/src/cpu/kvm/x86_cpu.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/kvm/x86_cpu.cc Thu Jan 22 05:00:53 2015 -0500
@@ -554,8 +554,6 @@
updateCPUID();
- io_req.setThreadContext(tc->contextId(), 0);
-
// TODO: Do we need to create an identity mapped TSS area? We
// should call kvm.vm.setTSSAddress() here in that case. It should
// only be needed for old versions of the virtualization
@@ -1346,8 +1344,9 @@
pAddr = X86ISA::x86IOAddress(port);
}
- io_req.setPhys(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
+ Request io_req(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
dataMasterId());
+ io_req.setThreadContext(tc->contextId(), 0);
const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
// Temporarily lock and migrate to the event queue of the
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/kvm/x86_cpu.hh
--- a/src/cpu/kvm/x86_cpu.hh Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/kvm/x86_cpu.hh Thu Jan 22 05:00:53 2015 -0500
@@ -234,9 +234,6 @@
*/
void handleIOMiscReg32(int miscreg);
- /** Reusable IO request */
- Request io_req;
-
/** Cached intersection of supported MSRs */
mutable Kvm::MSRIndexVector cachedMsrIntersection;
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/simple/timing.cc Thu Jan 22 05:00:53 2015 -0500
@@ -270,8 +270,7 @@
TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
bool read)
{
- PacketPtr pkt;
- buildPacket(pkt, req, read);
+ PacketPtr pkt = buildPacket(req, read);
pkt->dataDynamic<uint8_t>(data);
if (req->getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
@@ -354,10 +353,10 @@
advanceInst(fault);
}
-void
-TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
+PacketPtr
+TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
{
- pkt = read ? Packet::createRead(req) : Packet::createWrite(req);
+ return read ? Packet::createRead(req) : Packet::createWrite(req);
}
void
@@ -370,14 +369,13 @@
assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
- buildPacket(pkt1, req, read);
+ pkt1 = buildPacket(req, read);
return;
}
- buildPacket(pkt1, req1, read);
- buildPacket(pkt2, req2, read);
+ pkt1 = buildPacket(req1, read);
+ pkt2 = buildPacket(req2, read);
- req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(),
dataMasterId());
PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
pkt->dataDynamic<uint8_t>(data);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/simple/timing.hh Thu Jan 22 05:00:53 2015 -0500
@@ -137,7 +137,7 @@
void translationFault(const Fault &fault);
- void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
+ PacketPtr buildPacket(RequestPtr req, bool read);
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
RequestPtr req1, RequestPtr req2, RequestPtr req,
uint8_t *data, bool read);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/testers/memtest/memtest.cc
--- a/src/cpu/testers/memtest/memtest.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/cpu/testers/memtest/memtest.cc Thu Jan 22 05:00:53 2015 -0500
@@ -300,16 +300,16 @@
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
- Request *req = new Request();
+ Request *req = nullptr;
uint8_t *result = new uint8_t[8];
if (issueDmas) {
paddr &= ~((1 << dma_access_size) - 1);
- req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
+ req = new Request(paddr, 1 << dma_access_size, flags, masterId);
req->setThreadContext(id,0);
} else {
paddr &= ~((1 << access_size) - 1);
- req->setPhys(paddr, 1 << access_size, flags, masterId);
+ req = new Request(paddr, 1 << access_size, flags, masterId);
req->setThreadContext(id,0);
}
assert(req->getSize() == 1);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/cpu/testers/networktest/networktest.cc
--- a/src/cpu/testers/networktest/networktest.cc Tue Jan 20 14:15:28
2015 -0600
+++ b/src/cpu/testers/networktest/networktest.cc Thu Jan 22 05:00:53
2015 -0500
@@ -198,9 +198,6 @@
destination = dest_y*networkDimension + dest_x;
}
- Request *req = new Request();
- Request::Flags flags;
-
// The source of the packets is a cache.
// The destination of the packets is a directory.
// The destination bits are embedded in the address after byte-offset.
@@ -234,21 +231,24 @@
//
MemCmd::Command requestType;
+ Request *req = nullptr;
+ Request::Flags flags;
+
unsigned randomReqType = random_mt.random(0, 2);
if (randomReqType == 0) {
// generate packet for virtual network 0
requestType = MemCmd::ReadReq;
- req->setPhys(paddr, access_size, flags, masterId);
+ req = new Request(paddr, access_size, flags, masterId);
} else if (randomReqType == 1) {
// generate packet for virtual network 1
requestType = MemCmd::ReadReq;
flags.set(Request::INST_FETCH);
- req->setVirt(0, 0x0, access_size, flags, 0x0, masterId);
+ req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0, 0);
req->setPaddr(paddr);
} else { // if (randomReqType == 2)
// generate packet for virtual network 2
requestType = MemCmd::WriteReq;
- req->setPhys(paddr, access_size, flags, masterId);
+ req = new Request(paddr, access_size, flags, masterId);
}
req->setThreadContext(id,0);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/mem/port_proxy.cc
--- a/src/mem/port_proxy.cc Tue Jan 20 14:15:28 2015 -0600
+++ b/src/mem/port_proxy.cc Thu Jan 22 05:00:53 2015 -0500
@@ -43,11 +43,9 @@
void
PortProxy::readBlob(Addr addr, uint8_t *p, int size) const
{
- Request req;
-
for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
gen.next()) {
- req.setPhys(gen.addr(), gen.size(), 0, Request::funcMasterId);
+ Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
Packet pkt(&req, MemCmd::ReadReq);
pkt.dataStatic(p);
_port.sendFunctional(&pkt);
@@ -58,11 +56,9 @@
void
PortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
{
- Request req;
-
for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
gen.next()) {
- req.setPhys(gen.addr(), gen.size(), 0, Request::funcMasterId);
+ Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
Packet pkt(&req, MemCmd::WriteReq);
pkt.dataStaticConst(p);
_port.sendFunctional(&pkt);
diff -r e5936c2d53a0 -r e3fc6bc7f97e src/mem/request.hh
--- a/src/mem/request.hh Tue Jan 20 14:15:28 2015 -0600
+++ b/src/mem/request.hh Thu Jan 22 05:00:53 2015 -0500
@@ -198,6 +198,28 @@
VALID_CONTEXT_ID | VALID_THREAD_ID;
private:
+
+ /**
+ * Set up a physical (e.g. device) request in a previously
+ * allocated Request object.
+ */
+ void
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