changeset fae54a666162 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fae54a666162
description:
cpu: Put all CPU instruction tracers in a single file
diffstat:
src/arch/arm/ArmNativeTrace.py | 2 +-
src/arch/sparc/SparcNativeTrace.py | 2 +-
src/arch/x86/X86NativeTrace.py | 2 +-
src/cpu/BaseCPU.py | 2 +-
src/cpu/CPUTracers.py | 48 ++++++++++++++++++++++++++++++++++++++
src/cpu/ExeTracer.py | 36 ----------------------------
src/cpu/IntelTrace.py | 36 ----------------------------
src/cpu/NativeTrace.py | 37 -----------------------------
src/cpu/SConscript | 4 +--
9 files changed, 53 insertions(+), 116 deletions(-)
diffs (237 lines):
diff -r c3fd4c020e49 -r fae54a666162 src/arch/arm/ArmNativeTrace.py
--- a/src/arch/arm/ArmNativeTrace.py Sun Jan 25 07:22:05 2015 -0500
+++ b/src/arch/arm/ArmNativeTrace.py Sun Jan 25 07:22:17 2015 -0500
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
diff -r c3fd4c020e49 -r fae54a666162 src/arch/sparc/SparcNativeTrace.py
--- a/src/arch/sparc/SparcNativeTrace.py Sun Jan 25 07:22:05 2015 -0500
+++ b/src/arch/sparc/SparcNativeTrace.py Sun Jan 25 07:22:17 2015 -0500
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
diff -r c3fd4c020e49 -r fae54a666162 src/arch/x86/X86NativeTrace.py
--- a/src/arch/x86/X86NativeTrace.py Sun Jan 25 07:22:05 2015 -0500
+++ b/src/arch/x86/X86NativeTrace.py Sun Jan 25 07:22:17 2015 -0500
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Sun Jan 25 07:22:05 2015 -0500
+++ b/src/cpu/BaseCPU.py Sun Jan 25 07:22:17 2015 -0500
@@ -49,7 +49,7 @@
from XBar import CoherentXBar
from InstTracer import InstTracer
-from ExeTracer import ExeTracer
+from CPUTracers import ExeTracer
from MemObject import MemObject
from ClockDomain import *
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/CPUTracers.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/CPUTracers.py Sun Jan 25 07:22:17 2015 -0500
@@ -0,0 +1,48 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from InstTracer import InstTracer
+
+class ExeTracer(InstTracer):
+ type = 'ExeTracer'
+ cxx_class = 'Trace::ExeTracer'
+ cxx_header = "cpu/exetrace.hh"
+
+class IntelTrace(InstTracer):
+ type = 'IntelTrace'
+ cxx_class = 'Trace::IntelTrace'
+ cxx_header = "cpu/inteltrace.hh"
+
+class NativeTrace(ExeTracer):
+ abstract = True
+ type = 'NativeTrace'
+ cxx_class = 'Trace::NativeTrace'
+ cxx_header = 'cpu/nativetrace.hh'
+
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/ExeTracer.py
--- a/src/cpu/ExeTracer.py Sun Jan 25 07:22:05 2015 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from InstTracer import InstTracer
-
-class ExeTracer(InstTracer):
- type = 'ExeTracer'
- cxx_class = 'Trace::ExeTracer'
- cxx_header = "cpu/exetrace.hh"
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/IntelTrace.py
--- a/src/cpu/IntelTrace.py Sun Jan 25 07:22:05 2015 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from InstTracer import InstTracer
-
-class IntelTrace(InstTracer):
- type = 'IntelTrace'
- cxx_class = 'Trace::IntelTrace'
- cxx_header = "cpu/inteltrace.hh"
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/NativeTrace.py
--- a/src/cpu/NativeTrace.py Sun Jan 25 07:22:05 2015 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from ExeTracer import ExeTracer
-
-class NativeTrace(ExeTracer):
- abstract = True
- type = 'NativeTrace'
- cxx_class = 'Trace::NativeTrace'
- cxx_header = "cpu/nativetrace.hh"
diff -r c3fd4c020e49 -r fae54a666162 src/cpu/SConscript
--- a/src/cpu/SConscript Sun Jan 25 07:22:05 2015 -0500
+++ b/src/cpu/SConscript Sun Jan 25 07:22:17 2015 -0500
@@ -38,11 +38,9 @@
SimObject('CheckerCPU.py')
SimObject('BaseCPU.py')
+SimObject('CPUTracers.py')
SimObject('FuncUnit.py')
-SimObject('ExeTracer.py')
-SimObject('IntelTrace.py')
SimObject('IntrControl.py')
-SimObject('NativeTrace.py')
SimObject('TimingExpr.py')
Source('activity.cc')
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