changeset bb7cd7193edc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bb7cd7193edc
description:
config: Adjust DRAM channel interleaving defaults
This patch changes the DRAM channel interleaving default behaviour to
be more representative. The default address mapping (RoRaBaCoCh) moves
the channel bits towards the least significant bits, and uses 128 byte
as the default channel interleaving granularity.
These defaults can be overridden if desired, but should serve as a
sensible starting point for most use-cases.
diffstat:
configs/common/MemConfig.py | 18 +++++++++++-------
src/mem/DRAMCtrl.py | 2 +-
2 files changed, 12 insertions(+), 8 deletions(-)
diffs (72 lines):
diff -r e2f9644a7738 -r bb7cd7193edc configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Tue Feb 03 14:25:50 2015 -0500
+++ b/configs/common/MemConfig.py Tue Feb 03 14:25:52 2015 -0500
@@ -127,7 +127,7 @@
# Normal alias
_mem_aliases[alias] = target
-def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
+def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
"""
Helper function for creating a single memoy controller from the given
options. This function is invoked multiple times in config_mem function
@@ -135,9 +135,7 @@
"""
import math
- # The default behaviour is to interleave on cache line granularity
- cache_line_bit = int(math.log(cache_line_size, 2)) - 1
- intlv_low_bit = cache_line_bit
+ intlv_low_bit = int(math.log(intlv_size, 2))
# Create an instance so we can figure out the address
# mapping and row-buffer size
@@ -160,13 +158,13 @@
rowbuffer_size = ctrl.device_rowbuffer_size.value * \
ctrl.devices_per_rank.value
- intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
+ intlv_low_bit = int(math.log(rowbuffer_size, 2))
# We got all we need to configure the appropriate address
# range
ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
intlvHighBit = \
- intlv_low_bit + intlv_bits,
+ intlv_low_bit + intlv_bits - 1,
intlvBits = intlv_bits,
intlvMatch = i)
return ctrl
@@ -192,13 +190,19 @@
cls = get(options.mem_type)
mem_ctrls = []
+ # The default behaviour is to interleave memory channels on 128
+ # byte granularity, or cache line granularity if larger than 128
+ # byte. This value is based on the locality seen across a large
+ # range of workloads.
+ intlv_size = max(128, system.cache_line_size.value)
+
# For every range (most systems will only have one), create an
# array of controllers and set their parameters to match their
# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in xrange(nbr_mem_ctrls):
mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
- system.cache_line_size.value)
+ intlv_size)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(cls, m5.objects.DRAMCtrl) and \
diff -r e2f9644a7738 -r bb7cd7193edc src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py Tue Feb 03 14:25:50 2015 -0500
+++ b/src/mem/DRAMCtrl.py Tue Feb 03 14:25:52 2015 -0500
@@ -92,7 +92,7 @@
# scheduler, address map and page policy
mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
- addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
+ addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
page_policy = Param.PageManage('open_adaptive', "Page management policy")
# enforce a limit on the number of accesses per row
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