changeset 5935ab1ddd7a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5935ab1ddd7a
description:
config: Add XOR hashing to the DRAM channel interleaving
This patch uses the recently added XOR hashing capabilities for the
DRAM channel interleaving. This avoids channel biasing due to strided
access patterns.
diffstat:
configs/common/MemConfig.py | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diffs (26 lines):
diff -r f6c168692b20 -r 5935ab1ddd7a configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Tue Feb 03 14:25:54 2015 -0500
+++ b/configs/common/MemConfig.py Tue Feb 03 14:25:55 2015 -0500
@@ -137,6 +137,13 @@
import math
intlv_low_bit = int(math.log(intlv_size, 2))
+ # Use basic hashing for the channel selection, and preferably use
+ # the lower tag bits from the last level cache. As we do not know
+ # the details of the caches here, make an educated guess. 4 MByte
+ # 4-way associative with 64 byte cache lines is 6 offset bits and
+ # 14 index bits.
+ xor_low_bit = 20
+
# Create an instance so we can figure out the address
# mapping and row-buffer size
ctrl = cls()
@@ -165,6 +172,8 @@
ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
intlvHighBit = \
intlv_low_bit + intlv_bits - 1,
+ xorHighBit = \
+ xor_low_bit + intlv_bits - 1,
intlvBits = intlv_bits,
intlvMatch = i)
return ctrl
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