changeset 276da6265ab8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=276da6265ab8
description:
sim: Move the BaseTLB to src/arch/generic/
The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
diffstat:
src/arch/alpha/tlb.hh | 2 +-
src/arch/arm/stage2_lookup.hh | 1 -
src/arch/arm/tlb.hh | 2 +-
src/arch/generic/BaseTLB.py | 34 +++++++++
src/arch/generic/SConscript | 5 +
src/arch/generic/tlb.cc | 72 ++++++++++++++++++++
src/arch/generic/tlb.hh | 150 ++++++++++++++++++++++++++++++++++++++++++
src/arch/mips/tlb.hh | 2 +-
src/arch/power/tlb.hh | 2 +-
src/arch/sparc/tlb.hh | 2 +-
src/arch/x86/faults.hh | 2 +-
src/arch/x86/tlb.hh | 2 +-
src/cpu/base_dyn_inst.hh | 2 +-
src/cpu/checker/cpu.cc | 2 +-
src/cpu/translation.hh | 2 +-
src/sim/BaseTLB.py | 34 ---------
src/sim/SConscript | 3 -
src/sim/tlb.cc | 71 -------------------
src/sim/tlb.hh | 150 ------------------------------------------
19 files changed, 271 insertions(+), 269 deletions(-)
diffs (truncated from 758 to 300 lines):
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Feb 11 10:23:24 2015 -0500
+++ b/src/arch/alpha/tlb.hh Wed Feb 11 10:23:27 2015 -0500
@@ -39,10 +39,10 @@
#include "arch/alpha/pagetable.hh"
#include "arch/alpha/utility.hh"
#include "arch/alpha/vtophys.hh"
+#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/AlphaTLB.hh"
-#include "sim/tlb.hh"
class ThreadContext;
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/arm/stage2_lookup.hh
--- a/src/arch/arm/stage2_lookup.hh Wed Feb 11 10:23:24 2015 -0500
+++ b/src/arch/arm/stage2_lookup.hh Wed Feb 11 10:23:27 2015 -0500
@@ -47,7 +47,6 @@
#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
#include "mem/request.hh"
-#include "sim/tlb.hh"
class ThreadContext;
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Wed Feb 11 10:23:24 2015 -0500
+++ b/src/arch/arm/tlb.hh Wed Feb 11 10:23:27 2015 -0500
@@ -48,12 +48,12 @@
#include "arch/arm/pagetable.hh"
#include "arch/arm/utility.hh"
#include "arch/arm/vtophys.hh"
+#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "dev/dma_device.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
-#include "sim/tlb.hh"
class ThreadContext;
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/generic/BaseTLB.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/BaseTLB.py Wed Feb 11 10:23:27 2015 -0500
@@ -0,0 +1,34 @@
+# Copyright (c) 2008 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class BaseTLB(SimObject):
+ type = 'BaseTLB'
+ abstract = True
+ cxx_header = "arch/generic/tlb.hh"
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/generic/SConscript
--- a/src/arch/generic/SConscript Wed Feb 11 10:23:24 2015 -0500
+++ b/src/arch/generic/SConscript Wed Feb 11 10:23:27 2015 -0500
@@ -33,4 +33,9 @@
Source('decode_cache.cc')
Source('mmapped_ipr.cc')
+Source('tlb.cc')
+
+SimObject('BaseTLB.py')
+
+DebugFlag('TLB')
Source('pseudo_inst.cc')
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/generic/tlb.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/tlb.cc Wed Feb 11 10:23:27 2015 -0500
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/generic/tlb.hh"
+
+#include "cpu/thread_context.hh"
+#include "mem/page_table.hh"
+#include "sim/faults.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
+
+Fault
+GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
+{
+ if (FullSystem)
+ panic("Generic translation shouldn't be used in full system mode.\n");
+
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if(fault != NoFault)
+ return fault;
+
+ return NoFault;
+}
+
+void
+GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
+}
+
+Fault
+GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode)
const
+{
+ return NoFault;
+}
+
+void
+GenericTLB::demapPage(Addr vaddr, uint64_t asn)
+{
+ warn("Demapping pages in the generic TLB is unnecessary.\n");
+}
diff -r 1922f9d2ac01 -r 276da6265ab8 src/arch/generic/tlb.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/tlb.hh Wed Feb 11 10:23:27 2015 -0500
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_TLB_HH__
+#define __ARCH_GENERIC_TLB_HH__
+
+#include "base/misc.hh"
+#include "mem/request.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+class BaseMasterPort;
+
+class BaseTLB : public SimObject
+{
+ protected:
+ BaseTLB(const Params *p)
+ : SimObject(p)
+ {}
+
+ public:
+ enum Mode { Read, Write, Execute };
+
+ public:
+ virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+
+ /**
+ * Remove all entries from the TLB
+ */
+ virtual void flushAll() = 0;
+
+ /**
+ * Take over from an old tlb context
+ */
+ virtual void takeOverFrom(BaseTLB *otlb) = 0;
+
+ /**
+ * Get the table walker master port if present. This is used for
+ * migrating port connections during a CPU takeOverFrom()
+ * call. For architectures that do not have a table walker, NULL
+ * is returned, hence the use of a pointer rather than a
+ * reference.
+ *
+ * @return A pointer to the walker master port or NULL if not present
+ */
+ virtual BaseMasterPort* getMasterPort() { return NULL; }
+
+ void memInvalidate() { flushAll(); }
+
+ class Translation
+ {
+ public:
+ virtual ~Translation()
+ {}
+
+ /**
+ * Signal that the translation has been delayed due to a hw page table
+ * walk.
+ */
+ virtual void markDelayed() = 0;
+
+ /*
+ * The memory for this object may be dynamically allocated, and it may
+ * be responsible for cleaning itself up which will happen in this
+ * function. Once it's called, the object is no longer valid.
+ */
+ virtual void finish(const Fault &fault, RequestPtr req,
+ ThreadContext *tc, Mode mode) = 0;
+
+ /** This function is used by the page table walker to determine if it
+ * should translate the a pending request or if the underlying request
+ * has been squashed.
+ * @ return Is the instruction that requested this translation
squashed?
+ */
+ virtual bool squashed() const { return false; }
+ };
+};
+
+class GenericTLB : public BaseTLB
+{
+ protected:
+ GenericTLB(const Params *p)
+ : BaseTLB(p)
+ {}
+
+ public:
+ void demapPage(Addr vaddr, uint64_t asn);
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