changeset 22452667fd5c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=22452667fd5c
description:
cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there
was a lot of old cruft that could be removed. This patch cleans up the
tester, and also makes it more clear what the assumptions are. As part
of this simplification the reference functional memory is also
removed.
The regression configs using MemTest are updated to reflect the
changes, and the stats will be bumped in a separate patch. The example
config will be updated in a separate patch due to more extensive
re-work.
In a follow-on patch a new tester will be introduced that uses the
MemChecker to implement true sharing.
diffstat:
configs/example/memtest.py | 15 +-
src/cpu/testers/memtest/MemTest.py | 57 +++--
src/cpu/testers/memtest/memtest.cc | 363 +++++++++++++++---------------------
src/cpu/testers/memtest/memtest.hh | 170 ++++++++--------
tests/configs/memtest-filter.py | 12 +-
tests/configs/memtest-ruby.py | 16 +-
tests/configs/memtest.py | 11 +-
7 files changed, 289 insertions(+), 355 deletions(-)
diffs (truncated from 1018 to 300 lines):
diff -r 276da6265ab8 -r 22452667fd5c configs/example/memtest.py
--- a/configs/example/memtest.py Wed Feb 11 10:23:27 2015 -0500
+++ b/configs/example/memtest.py Wed Feb 11 10:23:28 2015 -0500
@@ -124,7 +124,7 @@
# build a list of prototypes, one for each level of treespec, starting
# at the end (last entry is tester objects)
-prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
+prototypes = [ MemTest(max_loads=options.maxloads,
percent_functional=options.functional,
percent_uncacheable=options.uncacheable,
progress_interval=options.progress) ]
@@ -146,12 +146,9 @@
prototypes.insert(0, next)
# system simulated
-system = System(funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentXBar(),
- physmem = SimpleMemory(latency = "100ns"),
+system = System(physmem = SimpleMemory(latency = "100ns"),
cache_line_size = block_size)
-
system.voltage_domain = VoltageDomain(voltage = '1V')
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
@@ -182,14 +179,10 @@
# we just built the MemTest objects
parent.cpu = objs
for t in objs:
- t.test = getattr(attach_obj, attach_port)
- t.functional = system.funcbus.slave
+ t.port = getattr(attach_obj, attach_port)
make_level(treespec, prototypes, system.physmem, "port")
-# connect reference memory to funcbus
-system.funcbus.master = system.funcmem.port
-
# -----------------------
# run simulation
# -----------------------
@@ -202,7 +195,7 @@
# The system port is never used in the tester so merely connect it
# to avoid problems
-root.system.system_port = root.system.funcbus.slave
+root.system.system_port = root.system.physmem.cpu_side_bus.slave
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')
diff -r 276da6265ab8 -r 22452667fd5c src/cpu/testers/memtest/MemTest.py
--- a/src/cpu/testers/memtest/MemTest.py Wed Feb 11 10:23:27 2015 -0500
+++ b/src/cpu/testers/memtest/MemTest.py Wed Feb 11 10:23:28 2015 -0500
@@ -1,3 +1,15 @@
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -25,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
+# Andreas Hansson
from MemObject import MemObject
from m5.params import *
@@ -33,26 +46,30 @@
class MemTest(MemObject):
type = 'MemTest'
cxx_header = "cpu/testers/memtest/memtest.hh"
- max_loads = Param.Counter(0, "number of loads to execute")
- atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
- memory_size = Param.Int(65536, "memory size")
- percent_dest_unaligned = Param.Percent(50,
- "percent of copy dest address that are unaligned")
- percent_reads = Param.Percent(65, "target read percentage")
- issue_dmas = Param.Bool(False, "this memtester should issue dma requests")
- percent_source_unaligned = Param.Percent(50,
- "percent of copy source address that are unaligned")
- percent_functional = Param.Percent(50, "percent of access that are
functional")
- percent_uncacheable = Param.Percent(10,
- "target uncacheable percentage")
+
+ # Interval of packet injection, the size of the memory range
+ # touched, and an optional stop condition
+ interval = Param.Cycles(1, "Interval between request packets")
+ size = Param.Unsigned(65536, "Size of memory region to use (bytes)")
+ max_loads = Param.Counter(0, "Number of loads to execute before exiting")
+
+ # Control the mix of packets and if functional accesses are part of
+ # the mix or not
+ percent_reads = Param.Percent(65, "Percentage reads")
+ percent_functional = Param.Percent(50, "Percentage functional accesses")
+ percent_uncacheable = Param.Percent(10, "Percentage uncacheable")
+
+ # Determine how often to print progress messages and what timeout
+ # to use for checking progress of both requests and responses
progress_interval = Param.Counter(1000000,
- "progress report interval (in accesses)")
- trace_addr = Param.Addr(0, "address to trace")
+ "Progress report interval (in accesses)")
+ progress_check = Param.Cycles(5000000, "Cycles before exiting " \
+ "due to lack of progress")
- test = MasterPort("Port to the memory system to test")
- functional = MasterPort("Port to the functional memory " \
- "used for verification")
- suppress_func_warnings = Param.Bool(False,
- "suppress warnings when functional accesses fail.\n")
- sys = Param.System(Parent.any, "System Parameter")
+ port = MasterPort("Port to the memory system")
+ system = Param.System(Parent.any, "System this tester is part of")
+ # Add the ability to supress error responses on functional
+ # accesses as Ruby needs this
+ suppress_func_warnings = Param.Bool(False, "Suppress warnings when "\
+ "functional accesses fail.")
diff -r 276da6265ab8 -r 22452667fd5c src/cpu/testers/memtest/memtest.cc
--- a/src/cpu/testers/memtest/memtest.cc Wed Feb 11 10:23:27 2015 -0500
+++ b/src/cpu/testers/memtest/memtest.cc Wed Feb 11 10:23:28 2015 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -27,173 +39,129 @@
*
* Authors: Erik Hallnor
* Steve Reinhardt
+ * Andreas Hansson
*/
-// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
-
-#include <iomanip>
-#include <set>
-#include <string>
-#include <vector>
-
-#include "base/misc.hh"
#include "base/random.hh"
#include "base/statistics.hh"
#include "cpu/testers/memtest/memtest.hh"
#include "debug/MemTest.hh"
#include "mem/mem_object.hh"
-#include "mem/packet.hh"
-#include "mem/port.hh"
-#include "mem/request.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
using namespace std;
-int TESTER_ALLOCATOR=0;
+unsigned int TESTER_ALLOCATOR = 0;
bool
MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
{
- memtest->completeRequest(pkt);
+ memtest.completeRequest(pkt);
return true;
}
void
MemTest::CpuPort::recvRetry()
{
- memtest->doRetry();
+ memtest.recvRetry();
}
-void
+bool
MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
- cachePort.sendAtomic(pkt);
+ port.sendAtomic(pkt);
completeRequest(pkt);
- }
- else if (!cachePort.sendTimingReq(pkt)) {
- DPRINTF(MemTest, "accessRetry setting to true\n");
-
- //
- // dma requests should never be retried
- //
- if (issueDmas) {
- panic("Nacked DMA requests are not supported\n");
- }
- accessRetry = true;
- retryPkt = pkt;
} else {
- if (issueDmas) {
- dmaOutstanding = true;
+ if (!port.sendTimingReq(pkt)) {
+ retryPkt = pkt;
+ return false;
}
}
-
+ return true;
}
MemTest::MemTest(const Params *p)
: MemObject(p),
tickEvent(this),
- cachePort("test", this),
- funcPort("functional", this),
- funcProxy(funcPort, p->sys->cacheLineSize()),
- retryPkt(NULL),
-// mainMem(main_mem),
-// checkMem(check_mem),
- size(p->memory_size),
+ noRequestEvent(this),
+ noResponseEvent(this),
+ port("port", *this),
+ retryPkt(nullptr),
+ size(p->size),
+ interval(p->interval),
percentReads(p->percent_reads),
percentFunctional(p->percent_functional),
percentUncacheable(p->percent_uncacheable),
- issueDmas(p->issue_dmas),
- masterId(p->sys->getMasterId(name())),
- blockSize(p->sys->cacheLineSize()),
+ masterId(p->system->getMasterId(name())),
+ blockSize(p->system->cacheLineSize()),
+ blockAddrMask(blockSize - 1),
progressInterval(p->progress_interval),
+ progressCheck(p->progress_check),
nextProgressMessage(p->progress_interval),
- percentSourceUnaligned(p->percent_source_unaligned),
- percentDestUnaligned(p->percent_dest_unaligned),
maxLoads(p->max_loads),
- atomic(p->atomic),
- suppress_func_warnings(p->suppress_func_warnings)
+ atomic(p->system->isAtomicMode()),
+ suppressFuncWarnings(p->suppress_func_warnings)
{
id = TESTER_ALLOCATOR++;
+ fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
+ blockSize - 1);
- // Needs to be masked off once we know the block size.
- traceBlockAddr = p->trace_addr;
baseAddr1 = 0x100000;
baseAddr2 = 0x400000;
uncacheAddr = 0x800000;
- blockAddrMask = blockSize - 1;
- traceBlockAddr = blockAddr(traceBlockAddr);
-
// set up counters
- noResponseCycles = 0;
numReads = 0;
numWrites = 0;
- schedule(tickEvent, 0);
- accessRetry = false;
- dmaOutstanding = false;
+ // kick things into action
+ schedule(tickEvent, curTick());
+ schedule(noRequestEvent, clockEdge(progressCheck));
+ schedule(noResponseEvent, clockEdge(progressCheck));
}
BaseMasterPort &
MemTest::getMasterPort(const std::string &if_name, PortID idx)
{
- if (if_name == "functional")
- return funcPort;
- else if (if_name == "test")
- return cachePort;
+ if (if_name == "port")
+ return port;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
