changeset 1a6785e37d81 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1a6785e37d81
description:
mem: Clarification of packet crossbar timings
This patch clarifies the packet timings annotated
when going through a crossbar.
The old 'firstWordDelay' is replaced by 'headerDelay' that represents
the delay associated to the delivery of the header of the packet.
The old 'lastWordDelay' is replaced by 'payloadDelay' that represents
the delay needed to processing the payload of the packet.
For now the uses and values remain identical. However, going forward
the payloadDelay will be additive, and not include the
headerDelay. Follow-on patches will make the headerDelay capture the
pipeline latency incurred in the crossbar, whereas the payloadDelay
will capture the additional serialisation delay.
diffstat:
src/arch/x86/pagetable_walker.cc | 2 +-
src/dev/io_device.cc | 2 +-
src/dev/pcidev.cc | 2 +-
src/dev/x86/intdev.hh | 2 +-
src/mem/bridge.cc | 4 ++--
src/mem/cache/cache_impl.hh | 28 ++++++++++++++--------------
src/mem/coherent_xbar.cc | 16 ++++++++--------
src/mem/dram_ctrl.cc | 2 +-
src/mem/dramsim2.cc | 2 +-
src/mem/external_slave.cc | 4 ++--
src/mem/noncoherent_xbar.cc | 8 ++++----
src/mem/packet.hh | 24 ++++++++++++------------
src/mem/simple_mem.cc | 2 +-
src/mem/xbar.cc | 24 ++++++++++++++----------
src/mem/xbar.hh | 4 ++--
15 files changed, 65 insertions(+), 61 deletions(-)
diffs (truncated from 466 to 300 lines):
diff -r c0979b2ebda5 -r 1a6785e37d81 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/arch/x86/pagetable_walker.cc Wed Feb 11 10:23:47 2015 -0500
@@ -601,7 +601,7 @@
assert(!read);
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
state = nextState;
nextState = Ready;
diff -r c0979b2ebda5 -r 1a6785e37d81 src/dev/io_device.cc
--- a/src/dev/io_device.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/dev/io_device.cc Wed Feb 11 10:23:47 2015 -0500
@@ -55,7 +55,7 @@
PioPort::recvAtomic(PacketPtr pkt)
{
// @todo: We need to pay for this and not just zero it out
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
const Tick delay(pkt->isRead() ? device->read(pkt) : device->write(pkt));
assert(pkt->isResponse() || pkt->isError());
diff -r c0979b2ebda5 -r 1a6785e37d81 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/dev/pcidev.cc Wed Feb 11 10:23:47 2015 -0500
@@ -80,7 +80,7 @@
assert(pkt->getAddr() >= configAddr &&
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
}
diff -r c0979b2ebda5 -r 1a6785e37d81 src/dev/x86/intdev.hh
--- a/src/dev/x86/intdev.hh Wed Feb 11 10:23:36 2015 -0500
+++ b/src/dev/x86/intdev.hh Wed Feb 11 10:23:47 2015 -0500
@@ -82,7 +82,7 @@
Tick recvMessage(PacketPtr pkt)
{
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
return device->recvMessage(pkt);
}
};
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/bridge.cc
--- a/src/mem/bridge.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/bridge.cc Wed Feb 11 10:23:47 2015 -0500
@@ -137,7 +137,7 @@
DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
// @todo: We need to pay for this and not just zero it out
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
@@ -181,7 +181,7 @@
if (!retryReq) {
// @todo: We need to pay for this and not just zero it out
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
}
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/cache/cache_impl.hh Wed Feb 11 10:23:47 2015 -0500
@@ -419,7 +419,7 @@
pkt->popSenderState();
delete rec;
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
// forwardLatency is set here because there is a response from an
// upper level cache.
memSidePort->schedTimingSnoopResp(pkt, clockEdge(forwardLatency));
@@ -486,7 +486,7 @@
// also reset the bus time that the original packet has
// not yet paid for
- snoop_pkt->firstWordDelay = snoop_pkt->lastWordDelay = 0;
+ snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
// make this an instantaneous express snoop, and let the
// other caches in the system know that the packet is
@@ -521,7 +521,7 @@
uncacheableFlush(pkt);
// @todo: someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
// writes go in write buffer, reads use MSHR,
// prefetches are acknowledged (responded to) and dropped
@@ -579,7 +579,7 @@
if (needsResponse) {
pkt->makeTimingResponse();
// @todo: Make someone pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
// In this case we are considering lat neglecting
// responseLatency, modelling hit latency just as
@@ -598,7 +598,7 @@
// miss
// @todo: Make someone pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
Addr blk_addr = blockAlign(pkt->getAddr());
MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure());
@@ -1146,8 +1146,8 @@
// from lower level caches/memory to an upper level cache or
// the core.
completion_time = clockEdge(responseLatency) +
- (transfer_offset ? pkt->lastWordDelay :
- pkt->firstWordDelay);
+ (transfer_offset ? pkt->payloadDelay :
+ pkt->headerDelay);
assert(!target->pkt->req->isUncacheable());
@@ -1163,14 +1163,14 @@
// from lower level caches/memory to an upper level cache or
// the core.
completion_time = clockEdge(responseLatency) +
- pkt->lastWordDelay;
+ pkt->payloadDelay;
target->pkt->req->setExtraData(0);
} else {
// not a cache fill, just forwarding response
// responseLatency is the latency of the return path
// from lower level cahces/memory to the core.
completion_time = clockEdge(responseLatency) +
- pkt->lastWordDelay;
+ pkt->payloadDelay;
if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getConstPtr<uint8_t>());
}
@@ -1190,7 +1190,7 @@
target->pkt->getAddr());
}
// reset the bus additional time as it is now accounted for
- target->pkt->firstWordDelay = target->pkt->lastWordDelay = 0;
+ target->pkt->headerDelay = target->pkt->payloadDelay = 0;
cpuSidePort->schedTimingResp(target->pkt, completion_time);
break;
@@ -1239,7 +1239,7 @@
mq = mshr->queue;
mq->markPending(mshr);
requestMemSideBus((RequestCause)mq->index, clockEdge() +
- pkt->lastWordDelay);
+ pkt->payloadDelay);
} else {
mq->deallocate(mshr);
if (wasFull && !mq->isFull()) {
@@ -1512,7 +1512,7 @@
}
// We pay for fillLatency here.
blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
- pkt->lastWordDelay;
+ pkt->payloadDelay;
return blk;
}
@@ -1548,7 +1548,7 @@
assert(req_pkt->isInvalidate() || pkt->sharedAsserted());
pkt->makeTimingResponse();
// @todo Make someone pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
if (pkt->isRead()) {
pkt->setDataFromBlock(blk_data, blkSize);
}
@@ -1599,7 +1599,7 @@
snoopPkt.pushSenderState(new ForwardResponseRecord());
// the snoop packet does not need to wait any additional
// time
- snoopPkt.firstWordDelay = snoopPkt.lastWordDelay = 0;
+ snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
cpuSidePort->sendTimingSnoopReq(&snoopPkt);
if (snoopPkt.memInhibitAsserted()) {
// cache-to-cache response from some upper cache
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/coherent_xbar.cc
--- a/src/mem/coherent_xbar.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/coherent_xbar.cc Wed Feb 11 10:23:47 2015 -0500
@@ -168,7 +168,7 @@
unsigned int pkt_cmd = pkt->cmdToIndex();
calcPacketTiming(pkt);
- Tick packetFinishTime = pkt->lastWordDelay + curTick();
+ Tick packetFinishTime = curTick() + pkt->payloadDelay;
// uncacheable requests need never be snooped
if (!pkt->req->isUncacheable() && !system->bypassCaches()) {
@@ -222,7 +222,7 @@
assert(!pkt->memInhibitAsserted());
// undo the calculation so we can check for 0 again
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
DPRINTF(CoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
src_port->name(), pkt->cmdString(), pkt->getAddr());
@@ -301,7 +301,7 @@
unsigned int pkt_cmd = pkt->cmdToIndex();
calcPacketTiming(pkt);
- Tick packetFinishTime = pkt->lastWordDelay + curTick();
+ Tick packetFinishTime = curTick() + pkt->payloadDelay;
if (snoopFilter && !pkt->req->isUncacheable() && !system->bypassCaches()) {
// let the snoop filter inspect the response and update its state
@@ -427,7 +427,7 @@
assert(!pkt->isExpressSnoop());
calcPacketTiming(pkt);
- Tick packetFinishTime = pkt->lastWordDelay + curTick();
+ Tick packetFinishTime = curTick() + pkt->payloadDelay;
// forward it either as a snoop response or a normal response
if (forwardAsSnoop) {
@@ -608,8 +608,8 @@
transDist[pkt_cmd]++;
}
- // @todo: Not setting first-word time
- pkt->lastWordDelay = response_latency;
+ // @todo: Not setting header time
+ pkt->payloadDelay = response_latency;
return response_latency;
}
@@ -648,8 +648,8 @@
snoops++;
}
- // @todo: Not setting first-word time
- pkt->lastWordDelay = snoop_response_latency;
+ // @todo: Not setting header time
+ pkt->payloadDelay = snoop_response_latency;
return snoop_response_latency;
}
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/dram_ctrl.cc Wed Feb 11 10:23:47 2015 -0500
@@ -879,7 +879,7 @@
assert(pkt->isResponse());
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
// queue the packet in the response queue to be sent out after
// the static latency has passed
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/dramsim2.cc
--- a/src/mem/dramsim2.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/dramsim2.cc Wed Feb 11 10:23:47 2015 -0500
@@ -270,7 +270,7 @@
assert(pkt->isResponse());
// @todo someone should pay for this
- pkt->firstWordDelay = pkt->lastWordDelay = 0;
+ pkt->headerDelay = pkt->payloadDelay = 0;
DPRINTF(DRAMSim2, "Queuing response for address %lld\n",
pkt->getAddr());
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/external_slave.cc
--- a/src/mem/external_slave.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/external_slave.cc Wed Feb 11 10:23:47 2015 -0500
@@ -124,8 +124,8 @@
StubSlavePort::ResponseEvent::process()
{
owner.responsePacket->makeResponse();
- owner.responsePacket->firstWordDelay = 0;
- owner.responsePacket->lastWordDelay = 0;
+ owner.responsePacket->headerDelay = 0;
+ owner.responsePacket->payloadDelay = 0;
if (owner.sendTimingResp(owner.responsePacket)) {
owner.responsePacket = NULL;
diff -r c0979b2ebda5 -r 1a6785e37d81 src/mem/noncoherent_xbar.cc
--- a/src/mem/noncoherent_xbar.cc Wed Feb 11 10:23:36 2015 -0500
+++ b/src/mem/noncoherent_xbar.cc Wed Feb 11 10:23:47 2015 -0500
@@ -128,7 +128,7 @@
unsigned int pkt_cmd = pkt->cmdToIndex();
calcPacketTiming(pkt);
- Tick packetFinishTime = pkt->lastWordDelay + curTick();
+ Tick packetFinishTime = curTick() + pkt->payloadDelay;
// before forwarding the packet (and possibly altering it),
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
