I'd like to remove the ExtMachInst concept from gem5, or at least hide it within the ISAs that need it. The only place where it isn't obvious how to do that is in the "Minor" cpu where it treats the ExtMachInst as a 64 bit integer (!) and masks it against a bit mask (!) to see when certain additional timing applies. This is really counter to the idea of what an ExtMachInst is in the first place, and also seems highly specific to ISAs where things are in particular places consistently and can be characterized with bit masks.
I'm not familiar with the Minor CPU, but it seems to me there must be a better way to handle this. Removing the idea of an ExtMachInst as an ISA external concept makes certain things easier and safer to do in the decoder, so I would really like to clean this up. A comment makes it sound like this is supposed to behave specially based on the source registers for an instruction. That information is already available from the StaticInst, so no bit fiddling with the ExtMachInst should be necessary. Gabe _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
