As the error message suggest you seem to have a packet that spans a cache line boundary. Have you checked the address and/or size to make sure they all are within a cache line?
Andreas On 26/02/2015 21:15, "Sensen Hu - EWI via gem5-dev" <[email protected]> wrote: >hi, Andreas. >I've tried to set Maxtick more than 16000. But in the command window, it >shows Aborted (core dumped). > >And the simerr file shows: > >gem5.opt: build/ARM/mem/cache/cache_impl.hh:164: void >Cache<TagStore>::satisfyCpuSideRequest(PacketPtr, >Cache<TagStore>::BlkType*, bool, bool) [with TagStore = LRU; PacketPtr = >Packet*; Cache<TagStore>::BlkType = CacheBlk]: Assertion >`pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed. >Program aborted at tick 57000 > >I adjusted the Maxtick and the duration (ticks) of tgen-simple-mem.cfg, I >got the same error. >So I don't know how to solve the error. > > >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
