changeset 890269a13188 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=890269a13188
description:
arm: Don't truncate 16-bit ASIDs to 8 bits
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers
and has a couple of inverted checks that mask out the high 8 bits of
an ASID if 16-bit ASIDs have been /enabled/. This changeset fixes both
of those issues.
diffstat:
src/arch/arm/isa.cc | 8 ++++----
src/arch/arm/isa.hh | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diffs (38 lines):
diff -r fe09d1bc6721 -r 890269a13188 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Mar 02 04:00:27 2015 -0500
+++ b/src/arch/arm/isa.cc Mon Mar 02 04:00:28 2015 -0500
@@ -1386,7 +1386,7 @@
oc = sys->getThreadContext(x);
assert(oc->getITBPtr() && oc->getDTBPtr());
asid = bits(newVal, 63, 48);
- if (haveLargeAsid64)
+ if (!haveLargeAsid64)
asid &= mask(8);
oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
@@ -1941,10 +1941,10 @@
}
void
-ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool
secure_lookup,
- uint8_t target_el)
+ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
+ bool secure_lookup, uint8_t target_el)
{
- if (haveLargeAsid64)
+ if (!haveLargeAsid64)
asid &= mask(8);
Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
System *sys = tc->getSystemPtr();
diff -r fe09d1bc6721 -r 890269a13188 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Mon Mar 02 04:00:27 2015 -0500
+++ b/src/arch/arm/isa.hh Mon Mar 02 04:00:28 2015 -0500
@@ -221,7 +221,7 @@
assert(!cpsr.width);
}
- void tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid,
+ void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
bool secure_lookup, uint8_t target_el);
void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
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