changeset 4cfe55719da5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4cfe55719da5
description:
mem: restructure Packet cmd initialization a bit more
Refactor the way that specific MemCmd values are generated for packets.
The new approach is a little more elegant in that we assign the right
value up front, and it's also more amenable to non-heap-allocated
Packet objects.
Also replaced the code in the Minor model that was still doing it the
ad-hoc way.
This is basically a refinement of
http://repo.gem5.org/gem5/rev/711eb0e64249.
diffstat:
src/cpu/inorder/resources/cache_unit.cc | 13 ++++++-
src/cpu/inorder/resources/cache_unit.hh | 4 +-
src/cpu/minor/lsq.cc | 14 +-------
src/cpu/simple/atomic.cc | 3 +-
src/mem/packet.hh | 50 +++++++++++++++++---------------
5 files changed, 41 insertions(+), 43 deletions(-)
diffs (157 lines):
diff -r a5f134ef30d3 -r 4cfe55719da5 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sat Mar 14 06:51:07 2015 -0700
+++ b/src/cpu/inorder/resources/cache_unit.cc Wed Feb 11 10:48:50 2015 -0800
@@ -811,10 +811,17 @@
void
CacheUnit::buildDataPacket(CacheRequest *cache_req)
{
- cache_req->dataPkt = new CacheReqPacket(cache_req,
- cache_req->pktCmd,
+ MemCmd cmd;
+
+ if (cache_req->pktCmd == MemCmd::ReadReq) {
+ cmd = Packet::makeReadCmd(cache_req->memReq);
+ } else {
+ assert(cache_req->pktCmd == MemCmd::WriteReq);
+ cmd = Packet::makeWriteCmd(cache_req->memReq);
+ }
+
+ cache_req->dataPkt = new CacheReqPacket(cache_req, cmd,
cache_req->instIdx);
- cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),
diff -r a5f134ef30d3 -r 4cfe55719da5 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Sat Mar 14 06:51:07 2015 -0700
+++ b/src/cpu/inorder/resources/cache_unit.hh Wed Feb 11 10:48:50 2015 -0800
@@ -230,7 +230,7 @@
bool isMemAccPending() { return memAccPending; }
//Make this data private/protected!
- MemCmd::Command pktCmd;
+ MemCmd pktCmd;
RequestPtr memReq;
PacketDataPtr reqData;
CacheReqPacket *dataPkt;
@@ -252,7 +252,7 @@
{
public:
CacheReqPacket(CacheRequest *_req,
- Command _cmd, int _idx = 0)
+ MemCmd _cmd, int _idx = 0)
: Packet(&(*_req->memReq), _cmd), cacheReq(_req),
instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
{
diff -r a5f134ef30d3 -r 4cfe55719da5 src/cpu/minor/lsq.cc
--- a/src/cpu/minor/lsq.cc Sat Mar 14 06:51:07 2015 -0700
+++ b/src/cpu/minor/lsq.cc Wed Feb 11 10:48:50 2015 -0800
@@ -1545,18 +1545,8 @@
makePacketForRequest(Request &request, bool isLoad,
Packet::SenderState *sender_state, PacketDataPtr data)
{
- MemCmd command;
-
- /* Make a ret with the right command type to match the request */
- if (request.isLLSC()) {
- command = (isLoad ? MemCmd::LoadLockedReq : MemCmd::StoreCondReq);
- } else if (request.isSwap()) {
- command = MemCmd::SwapReq;
- } else {
- command = (isLoad ? MemCmd::ReadReq : MemCmd::WriteReq);
- }
-
- PacketPtr ret = new Packet(&request, command);
+ PacketPtr ret = isLoad ? Packet::createRead(&request)
+ : Packet::createWrite(&request);
if (sender_state)
ret->pushSenderState(sender_state);
diff -r a5f134ef30d3 -r 4cfe55719da5 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sat Mar 14 06:51:07 2015 -0700
+++ b/src/cpu/simple/atomic.cc Wed Feb 11 10:48:50 2015 -0800
@@ -341,8 +341,7 @@
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt(req, MemCmd::ReadReq);
- pkt.refineCommand();
+ Packet pkt(req, Packet::makeReadCmd(req));
pkt.dataStatic(data);
if (req->isMmappedIpr())
diff -r a5f134ef30d3 -r 4cfe55719da5 src/mem/packet.hh
--- a/src/mem/packet.hh Sat Mar 14 06:51:07 2015 -0700
+++ b/src/mem/packet.hh Wed Feb 11 10:48:50 2015 -0800
@@ -643,45 +643,47 @@
}
/**
- * Change the packet type based on request type.
+ * Generate the appropriate read MemCmd based on the Request flags.
*/
- void
- refineCommand()
+ static MemCmd
+ makeReadCmd(const RequestPtr req)
{
- if (cmd == MemCmd::ReadReq) {
- if (req->isLLSC()) {
- cmd = MemCmd::LoadLockedReq;
- } else if (req->isPrefetch()) {
- cmd = MemCmd::SoftPFReq;
- }
- } else if (cmd == MemCmd::WriteReq) {
- if (req->isLLSC()) {
- cmd = MemCmd::StoreCondReq;
- } else if (req->isSwap()) {
- cmd = MemCmd::SwapReq;
- }
- }
+ if (req->isLLSC())
+ return MemCmd::LoadLockedReq;
+ else if (req->isPrefetch())
+ return MemCmd::SoftPFReq;
+ else
+ return MemCmd::ReadReq;
+ }
+
+ /**
+ * Generate the appropriate write MemCmd based on the Request flags.
+ */
+ static MemCmd
+ makeWriteCmd(const RequestPtr req)
+ {
+ if (req->isLLSC())
+ return MemCmd::StoreCondReq;
+ else if (req->isSwap())
+ return MemCmd::SwapReq;
+ else
+ return MemCmd::WriteReq;
}
/**
* Constructor-like methods that return Packets based on Request objects.
- * Will call refineCommand() to fine-tune the Packet type if it's not a
- * vanilla read or write.
+ * Fine-tune the MemCmd type if it's not a vanilla read or write.
*/
static PacketPtr
createRead(const RequestPtr req)
{
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
- pkt->refineCommand();
- return pkt;
+ return new Packet(req, makeReadCmd(req));
}
static PacketPtr
createWrite(const RequestPtr req)
{
- PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
- pkt->refineCommand();
- return pkt;
+ return new Packet(req, makeWriteCmd(req));
}
/**
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