Hello
I am trying to boot a quadcore system (1 core per cluster| 4 clusters |
per-core DVFS support | *dts file attached w**ith e-mail*) with
arm_detailed CPU model. I am running with DVFS enabled linux-linaro gem5
specific kernel configured for ondemand governor. I am using the disk
image ARMv7a-ICS-Android.SMP.Asimbench-v3.img that comes with asimbench.
The simulation panics wih following message:
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
82292307048: system.cpu1.break_event: break event panic triggered
82292308476: system.cpu1.break_event: break event panic triggered
82292308476: system.cpu1.break_event: break event panic triggered
82292308476: system.cpu1.break_event: break event panic triggered
82292308476: system.cpu1.break_event: break event panic triggered
The *system.terminal output (fi**le attached with the email)* is stuck
at following point:
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS
(lpj=19988480)
52 ^Mpid_max: default: 32768 minimum: 301
53 ^MMount-cache hash table entries: 512
54 ^MCPU: Testing write buffer coherency: ok
55 ^MCPU0: update cpu_power 1024
56 ^MCPU0: thread -1, cpu 0, socket 0, mpidr 80000000
57 ^MSetting up static identity map for 0x8043d988 - 0x8043d9bc
58 ^M[<80015844>] (unwind_backtrace+0x0/0xf8) from [<80011d20>]
(show_stack+0x10/0x14)
59 ^M[<80011d20>] (show_stack+0x10/0x14) from [<80439214>]
(dump_stack+0x74/0xb4)
60 ^M[<80439214>] (dump_stack+0x74/0xb4) from [<80014840>]
(handle_IPI+0x194/0x1c8)
61 ^M[<80014840>] (handle_IPI+0x194/0x1c8) from [<80008598>]
(gic_handle_irq+0x54/0x5c)
62 ^M[<80008598>] (gic_handle_irq+0x54/0x5c) from [<80012800>]
(__irq_svc+0x40/0x70)
63 ^MException stack(0x9f843ea0 to 0x9f843ee8)
64 ^M3ea0: 001f99f9 00000000 ea15aaf8 8033ae48 806972f4 000000fb
001f995c 80630eb0
65 ^M3ec0: 8061a414 00000000 9f875400 00000000 00000002 9f843ee8
800152b4 8033ae4c
66 ^M3ee0: a0000113 ffffffff
67 ^M[<80012800>] (__irq_svc+0x40/0x70) from [<8033ae4c>]
(arch_counter_get_cntvct+0x4/0xc)
68 ^M[<8033ae4c>] (arch_counter_get_cntvct+0x4/0xc) from [<800152b4>]
(arch_timer_read_counter_long+0x14/0x18)
69 ^M[<800152b4>] (arch_timer_read_counter_long+0x14/0x18) from
[<8021fc54>] (__timer_delay+0x48/0x5c)
70 ^M[<8021fc54>] (__timer_delay+0x48/0x5c) from [<8001fa64>]
(versatile_boot_secondary+0x94/0xd8)
71 ^M[<8001fa64>] (versatile_boot_secondary+0x94/0xd8) from
[<8001406c>] (__cpu_up+0xa4/0x168)
72 ^M[<8001406c>] (__cpu_up+0xa4/0x168) from [<80022adc>]
(cpu_up+0xe4/0x188)
73 ^M[<80022adc>] (cpu_up+0xe4/0x188) from [<805d7368>]
(smp_init+0x68/0xac)
74 ^M[<805d7368>] (smp_init+0x68/0xac) from [<805c9bc4>]
(kernel_init_freeable+0xd0/0x22c)
75 ^M[<805c9bc4>] (kernel_init_freeable+0xd0/0x22c) from [<80433d14>]
(kernel_init+0x8/0x110)
76 ^M[<80433d14>] (kernel_init+0x8/0x110) from [<8000e378>]
(ret_from_fork+0x14/0x3c)
Interestingly, the *problem goes away when I change my CPU model in
commandline from "arm_detailed" to "detailed"*. Does anyone have any
ideas on this? I was under the impression that arm_detailed cpu was
different from detailed CPU only in size of certain resources like
buffer sizes, ALUs etc; but it seems there is more to it!
Further, I am *able to boot with arm_detailed cpu with a single core*.
Would really appreciate any help on understanding and resolving this issue!
--
Regards
Lokesh Jindal
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.13.0-rc2-00001-ga75e551-dirty (ljindal@bigbird) (gcc version
4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5) ) #24 SMP PREEMPT Wed Jan 21 14:10:45 CST
2015
Kernel was built at commit id 'a75e551'
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: V2P-CA15
bootconsole [earlycon0] enabled
Memory policy: Data cache writealloc
kdebugv2m: Following are test values to confirm proper working
kdebugv2m: Ranges 42000000 0
kdebugv2m: Regs 30000000 1000000
kdebugv2m: Virtual-Reg f0000000
kdebugv2m: pci node addr_cells 3
kdebugv2m: pci node size_cells 2
kdebugv2m: motherboard addr_cells 2
On node 0 totalpages: 131072
free_area_init_node: node 0, pgdat 806485c0, node_mem_map 806a7000
Normal zone: 1024 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 131072 pages, LIFO batch:31
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
PERCPU: Embedded 8 pages/cpu @80ab0000 s12160 r8192 d12416 u32768
pcpu-alloc: s12160 r8192 d12416 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480
norandmaps rw loglevel=8 mem=512MB root=/dev/sda1 init=/init
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 496408K/524288K available (4469K kernel code, 236K rwdata, 1420K
rodata, 287K init, 358K bss, 27880K reserved, 0K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xa0800000 - 0xff000000 (1512 MB)
lowmem : 0x80000000 - 0xa0000000 ( 512 MB)
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
.text : 0x80008000 - 0x805c8a08 (5891 kB)
.init : 0x805c9000 - 0x80610f80 ( 288 kB)
.data : 0x80612000 - 0x8064d16c ( 237 kB)
.bss : 0x8064d16c - 0x806a6c90 ( 359 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Preemptible hierarchical RCU implementation.
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
NR_IRQS:16 nr_irqs:16 16
Architected cp15 timer(s) running at 25.16MHz (phys).
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
Switching to timer-based delay loop
Console: colour dummy device 80x30
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: update cpu_power 1024
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x8043d988 - 0x8043d9bc
[<80015844>] (unwind_backtrace+0x0/0xf8) from [<80011d20>]
(show_stack+0x10/0x14)
[<80011d20>] (show_stack+0x10/0x14) from [<80439214>] (dump_stack+0x74/0xb4)
[<80439214>] (dump_stack+0x74/0xb4) from [<80014840>] (handle_IPI+0x194/0x1c8)
[<80014840>] (handle_IPI+0x194/0x1c8) from [<80008598>]
(gic_handle_irq+0x54/0x5c)
[<80008598>] (gic_handle_irq+0x54/0x5c) from [<80012800>] (__irq_svc+0x40/0x70)
Exception stack(0x9f843ea0 to 0x9f843ee8)
3ea0: 001f99f9 00000000 ea15aaf8 8033ae48 806972f4 000000fb 001f995c 80630eb0
3ec0: 8061a414 00000000 9f875400 00000000 00000002 9f843ee8 800152b4 8033ae4c
3ee0: a0000113 ffffffff
[<80012800>] (__irq_svc+0x40/0x70) from [<8033ae4c>]
(arch_counter_get_cntvct+0x4/0xc)
[<8033ae4c>] (arch_counter_get_cntvct+0x4/0xc) from [<800152b4>]
(arch_timer_read_counter_long+0x14/0x18)
[<800152b4>] (arch_timer_read_counter_long+0x14/0x18) from [<8021fc54>]
(__timer_delay+0x48/0x5c)
[<8021fc54>] (__timer_delay+0x48/0x5c) from [<8001fa64>]
(versatile_boot_secondary+0x94/0xd8)
[<8001fa64>] (versatile_boot_secondary+0x94/0xd8) from [<8001406c>]
(__cpu_up+0xa4/0x168)
[<8001406c>] (__cpu_up+0xa4/0x168) from [<80022adc>] (cpu_up+0xe4/0x188)
[<80022adc>] (cpu_up+0xe4/0x188) from [<805d7368>] (smp_init+0x68/0xac)
[<805d7368>] (smp_init+0x68/0xac) from [<805c9bc4>]
(kernel_init_freeable+0xd0/0x22c)
[<805c9bc4>] (kernel_init_freeable+0xd0/0x22c) from [<80433d14>]
(kernel_init+0x8/0x110)
[<80433d14>] (kernel_init+0x8/0x110) from [<8000e378>] (ret_from_fork+0x14/0x3c)
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A15x2 (version with Test Chip 1)
* Cortex-A15 MPCore (V2P-CA15)
*
* HBI-0237A
*/
/dts-v1/;
/memreserve/ 0x8f000000 0x01000000;
/ {
model = "V2P-CA15";
arm,hbi = <0x0>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15",
"arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
clusters {
#address-cells = <1>;
#size-cells = <0>;
cluster0: cluster@0 {
reg = <0>;
cores {
#address-cells = <1>;
#size-cells = <0>;
core0: core@0 {
reg = <0>;
};
};
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
cluster = <&cluster0>;
core = <&core0>;
clock-frequency = <1000000000>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0 0x2b0a0000 0 0x1000>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
wdt@2b060000 {
compatible = "arm,sp805", "arm,primecell";
status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
/*
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
dma@7ffb0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0 0x7ffb0000 0 0x1000>;
interrupts = <0 92 4>,
<0 88 4>,
<0 89 4>,
<0 90 4>,
<0 91 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
*/
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>;
clocks = <&oscclk7>;
clock-names="apb_pclk";
};
/** HACK : cortex-a9-twd-timer hack -- temporary fix */
/*timer@2c080000 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0 0x2c080000 0 0x20>;
interrupts = <1 13 0xf04>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};*/
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
/* CPU PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <50000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk0";
};
osc@4 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <20000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk4";
};
oscclk5: osc@5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
// freq-range = <23750000 165000000>; // original
freq-range = <23750000 1000000000>; // for gem5
extended
// resolution
support
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
smbclk: osc@6 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
freq-range = <20000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk6";
};
oscclk7: osc@7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
freq-range = <20000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk7";
};
osc@8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
freq-range = <40000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk8";
};
volt@0 {
/* CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "Cores";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
label = "Cores";
};
amp@0 {
/* Total current for the two cores */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 0>;
label = "Cores";
};
temp@0 {
/* DCC internal temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
power@0 {
/* Total power */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 0>;
label = "Cores";
};
energy@0 {
/* Total energy */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>;
label = "Cores";
};
};
smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
/include/ "vexpress-v2m-rs1-gem5.dtsi"
};
};
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