changeset a3cf53cd17b1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a3cf53cd17b1
description:
arm: Remove the 'magic MSI register' in the GIC (PL390)
This patch removes the code that added this magic register. A
follow-up patch provides a GICv2m MSI shim that gives the same
functionality in a standard ARM system architecture way.
diffstat:
src/dev/arm/Gic.py | 1 -
src/dev/arm/gic_pl390.cc | 63 +-----------------------------------------------
src/dev/arm/gic_pl390.hh | 18 -------------
3 files changed, 1 insertions(+), 81 deletions(-)
diffs (182 lines):
diff -r 3fe41011333d -r a3cf53cd17b1 src/dev/arm/Gic.py
--- a/src/dev/arm/Gic.py Thu Mar 19 04:06:14 2015 -0400
+++ b/src/dev/arm/Gic.py Thu Mar 19 04:06:16 2015 -0400
@@ -54,7 +54,6 @@
dist_addr = Param.Addr(0x1f001000, "Address for distributor")
cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
- msix_addr = Param.Addr(0x0, "Address for MSI-X register")
dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
diff -r 3fe41011333d -r a3cf53cd17b1 src/dev/arm/gic_pl390.cc
--- a/src/dev/arm/gic_pl390.cc Thu Mar 19 04:06:14 2015 -0400
+++ b/src/dev/arm/gic_pl390.cc Thu Mar 19 04:06:16 2015 -0400
@@ -55,9 +55,7 @@
: BaseGic(p), distAddr(p->dist_addr),
cpuAddr(p->cpu_addr), distPioDelay(p->dist_pio_delay),
cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
- enabled(false), itLines(p->it_lines), irqEnable(false),
- msixRegAddr(p->msix_addr),
- msixReg(0x0)
+ enabled(false), itLines(p->it_lines), irqEnable(false)
{
itLinesLog2 = ceilLog2(itLines);
@@ -113,10 +111,6 @@
return readDistributor(pkt);
else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
return readCpu(pkt);
- else if (msixRegAddr != 0x0 &&
- addr >= msixRegAddr &&
- addr < msixRegAddr + MSIX_SIZE)
- return readMsix(pkt);
else
panic("Read to unknown address %#x\n", pkt->getAddr());
}
@@ -132,10 +126,6 @@
return writeDistributor(pkt);
else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
return writeCpu(pkt);
- else if (msixRegAddr != 0x0 &&
- addr >= msixRegAddr &&
- addr < msixRegAddr + MSIX_SIZE)
- return writeMsix(pkt);
else
panic("Write to unknown address %#x\n", pkt->getAddr());
}
@@ -358,26 +348,6 @@
}
Tick
-Pl390::readMsix(PacketPtr pkt)
-{
- Addr daddr = pkt->getAddr() - msixRegAddr;
-
- DPRINTF(GIC, "Gic MSIX read register %#x\n", daddr);
-
- switch (daddr) {
- case MSIX_SR:
- pkt->set<uint32_t>(msixReg);
- break;
- default:
- panic("Tried to read Gic MSIX register at offset %#x\n", daddr);
- break;
- }
-
- pkt->makeAtomicResponse();
- return distPioDelay;
-}
-
-Tick
Pl390::writeDistributor(PacketPtr pkt)
{
Addr daddr = pkt->getAddr() - distAddr;
@@ -571,30 +541,6 @@
return cpuPioDelay;
}
-Tick
-Pl390::writeMsix(PacketPtr pkt)
-{
- Addr daddr = pkt->getAddr() - msixRegAddr;
-
- DPRINTF(GIC, "Gic MSI-X write register %#x data %d\n",
- daddr, pkt->get<uint32_t>());
-
- switch (daddr) {
- case MSIX_SR:
- // This value is little endian, just like the ARM guest
- msixReg = pkt->get<uint32_t>();
- pendingInt[intNumToWord(letoh(msixReg))] |= 1UL <<
intNumToBit(letoh(msixReg));
- updateIntState(-1);
- break;
- default:
- panic("Tried to write Gic MSI-X register at offset %#x\n", daddr);
- break;
- }
-
- pkt->makeAtomicResponse();
- return distPioDelay;
-}
-
void
Pl390::softInt(int ctx_id, SWI swi)
{
@@ -786,9 +732,6 @@
AddrRangeList ranges;
ranges.push_back(RangeSize(distAddr, DIST_SIZE));
ranges.push_back(RangeSize(cpuAddr, CPU_SIZE));
- if (msixRegAddr != 0) {
- ranges.push_back(RangeSize(msixRegAddr, MSIX_SIZE));
- }
return ranges;
}
@@ -805,8 +748,6 @@
SERIALIZE_SCALAR(enabled);
SERIALIZE_SCALAR(itLines);
SERIALIZE_SCALAR(itLinesLog2);
- SERIALIZE_SCALAR(msixRegAddr);
- SERIALIZE_SCALAR(msixReg);
SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
SERIALIZE_ARRAY(activeInt, INT_BITS_MAX);
@@ -847,8 +788,6 @@
UNSERIALIZE_SCALAR(enabled);
UNSERIALIZE_SCALAR(itLines);
UNSERIALIZE_SCALAR(itLinesLog2);
- UNSERIALIZE_SCALAR(msixRegAddr);
- UNSERIALIZE_SCALAR(msixReg);
UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX);
diff -r 3fe41011333d -r a3cf53cd17b1 src/dev/arm/gic_pl390.hh
--- a/src/dev/arm/gic_pl390.hh Thu Mar 19 04:06:14 2015 -0400
+++ b/src/dev/arm/gic_pl390.hh Thu Mar 19 04:06:16 2015 -0400
@@ -113,10 +113,6 @@
static const int INT_BITS_MAX = 32;
static const int INT_LINES_MAX = 1020;
- /** MSI-X register offset and size */
- static const int MSIX_SR = 0x0; // MSI register devices will write to
- static const int MSIX_SIZE = 0x4; // Size of MSI-X register space
-
BitUnion32(SWI)
Bitfield<3,0> sgi_id;
Bitfield<23,16> cpu_list;
@@ -211,10 +207,6 @@
/** IRQ Enable Used for debug */
bool irqEnable;
- /** MSIX Register */
- Addr msixRegAddr;
- uint32_t msixReg;
-
/** software generated interrupt
* @param data data to decode that indicates which cpus to interrupt
*/
@@ -322,11 +314,6 @@
*/
Tick readCpu(PacketPtr pkt);
- /** Handle a read to the MSI-X register on the GIC
- * @param pkt packet to respond to
- */
- Tick readMsix(PacketPtr pkt);
-
/** Handle a write to the distributor poriton of the GIC
* @param pkt packet to respond to
*/
@@ -336,11 +323,6 @@
* @param pkt packet to respond to
*/
Tick writeCpu(PacketPtr pkt);
-
- /** Handle a write to the MSI-X register on the GIC
- * @param pkt packet to process
- */
- Tick writeMsix(PacketPtr pkt);
};
#endif //__DEV_ARM_GIC_H__
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