> On March 23, 2015, 6:13 p.m., Steve Reinhardt wrote: > > src/mem/cache/cache_impl.hh, line 529 > > <http://reviews.gem5.org/r/2703/diff/1/?file=44266#file44266line529> > > > > how about just creating a block here (from before this decl to after > > the loop) to localize the scope of 'writebacks', so we don't have to bother > > with the assert at the bottom?
Could do if you think it makes things prettier. I think I'd rather create a new variable with a different name if you think it is needed. > On March 23, 2015, 6:13 p.m., Steve Reinhardt wrote: > > src/mem/cache/cache_impl.hh, line 893 > > <http://reviews.gem5.org/r/2703/diff/1/?file=44266#file44266line893> > > > > comment is wrong, we're issuing the writebacks (no write buffer in > > atomic mode) Will fix. > On March 23, 2015, 6:13 p.m., Steve Reinhardt wrote: > > src/mem/cache/cache_impl.hh, line 1440 > > <http://reviews.gem5.org/r/2703/diff/1/?file=44266#file44266line1440> > > > > looks like these were the only uses of writebackVisitor() and > > invalidateVisitor()... should we get rid of them? TBH I missed when they > > were introduced. We do memWriteback and memInvalidate when checkpointing and switching CPU models. Hence, they are still needed. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2703/#review5963 ----------------------------------------------------------- On March 22, 2015, 7:35 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2703/ > ----------------------------------------------------------- > > (Updated March 22, 2015, 7:35 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10765:3628e18edb65 > --------------------------- > mem: Allocate cache writebacks before new MSHRs > > This patch changes the order of writeback allocation such that any > writebacks resulting from a tag lookup (e.g. for an uncacheable > access), are added to the writebuffer before any new MSHR entries are > allocated. This ensures that the writebacks logically precedes the new > allocations. > > The patch also changes the uncacheable flush to use proper timed (or > atomic) writebacks, as opposed to functional writes. > > > Diffs > ----- > > src/mem/cache/cache.hh 48a72150f82c > src/mem/cache/cache_impl.hh 48a72150f82c > > Diff: http://reviews.gem5.org/r/2703/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
