changeset 8f5993cfa916 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8f5993cfa916
description:
mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
Makes x86-style locked operations even more distinct from
LLSC operations. Using "locked" by itself should be
obviously ambiguous now.
diffstat:
src/arch/x86/isa/microops/ldstop.isa | 4 ++--
src/cpu/simple/atomic.cc | 4 ++--
src/mem/request.hh | 4 ++--
src/mem/ruby/system/Sequencer.cc | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diffs (75 lines):
diff -r 37fd40f8300f -r 8f5993cfa916 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Mon Mar 23 16:14:19 2015 -0700
+++ b/src/arch/x86/isa/microops/ldstop.isa Mon Mar 23 16:14:20 2015 -0700
@@ -409,7 +409,7 @@
'(StoreCheck << FlagShift)')
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
'Data = Mem & mask(dataSize * 8);',
- '(StoreCheck << FlagShift) | Request::LOCKED')
+ '(StoreCheck << FlagShift) | Request::LOCKED_RMW')
defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
@@ -461,7 +461,7 @@
defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
- mem_flags="Request::LOCKED")
+ mem_flags="Request::LOCKED_RMW")
defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
diff -r 37fd40f8300f -r 8f5993cfa916 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Mon Mar 23 16:14:19 2015 -0700
+++ b/src/cpu/simple/atomic.cc Mon Mar 23 16:14:20 2015 -0700
@@ -373,7 +373,7 @@
//If we don't need to access a second cache line, stop now.
if (secondAddr <= addr)
{
- if (req->isLocked() && fault == NoFault) {
+ if (req->isLockedRMW() && fault == NoFault) {
assert(!locked);
locked = true;
}
@@ -480,7 +480,7 @@
//stop now.
if (fault != NoFault || secondAddr <= addr)
{
- if (req->isLocked() && fault == NoFault) {
+ if (req->isLockedRMW() && fault == NoFault) {
assert(locked);
locked = false;
}
diff -r 37fd40f8300f -r 8f5993cfa916 src/mem/request.hh
--- a/src/mem/request.hh Mon Mar 23 16:14:19 2015 -0700
+++ b/src/mem/request.hh Mon Mar 23 16:14:20 2015 -0700
@@ -127,7 +127,7 @@
* made up of a locked load, some operation on the data, and then a locked
* store.
*/
- static const FlagsType LOCKED = 0x00100000;
+ static const FlagsType LOCKED_RMW = 0x00100000;
/** The request is a Load locked/store conditional. */
static const FlagsType LLSC = 0x00200000;
/** This request is for a memory swap. */
@@ -626,7 +626,7 @@
bool isPrefetch() const { return _flags.isSet(PREFETCH); }
bool isLLSC() const { return _flags.isSet(LLSC); }
bool isPriv() const { return _flags.isSet(PRIVILEGED); }
- bool isLocked() const { return _flags.isSet(LOCKED); }
+ bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
diff -r 37fd40f8300f -r 8f5993cfa916 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Mon Mar 23 16:14:19 2015 -0700
+++ b/src/mem/ruby/system/Sequencer.cc Mon Mar 23 16:14:20 2015 -0700
@@ -604,7 +604,7 @@
primary_type = RubyRequestType_Load_Linked;
}
secondary_type = RubyRequestType_ATOMIC;
- } else if (pkt->req->isLocked()) {
+ } else if (pkt->req->isLockedRMW()) {
//
// x86 locked instructions are translated to store cache coherence
// requests because these requests should always be treated as read
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