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(Updated March 24, 2015, 5:29 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10768:9baf8f724c34 --------------------------- mem: Cleanup flow for uncacheable accesses This patch simplifies the code dealing with uncacheable timing accesses, aiming to align it with the existing miss handling. Similar to what we do in atomic, a timing request now goes through Cache::access (where the block is also flushed), and then proceeds to ignore any existing MSHR for the block in question. This unifies the flow for cacheable and uncacheable accesses, and for atomic and timing. Diffs (updated) ----- src/mem/cache/cache_impl.hh 8f5993cfa916 Diff: http://reviews.gem5.org/r/2698/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
