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Ship it! Ship It! - Andreas Hansson On March 25, 2015, 3:50 p.m., Nikos Nikoleris wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2707/ > ----------------------------------------------------------- > > (Updated March 25, 2015, 3:50 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10762:5eafde60758e > --------------------------- > cpu: fix system total instructions accounting > > The totalInstructions counter is only incremented when the whole > instruction is commited and not on every microop. It was incorrectly > reset in atomic and timing cpus. > > > Diffs > ----- > > src/cpu/o3/cpu.cc 37fd40f8300f > src/cpu/simple/atomic.cc 37fd40f8300f > src/cpu/simple/timing.cc 37fd40f8300f > src/cpu/minor/execute.cc 37fd40f8300f > > Diff: http://reviews.gem5.org/r/2707/diff/ > > > Testing > ------- > > build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing CHANGED > > Maximum error magnitude: +0.001333% > > Reference New Value Abs Diff Pct Chg > Key statistics: > > host_inst_rate 858252 701692 -156560 -18.24% > host_mem_usage 653812 601288 -52524 -8.03% > sim_insts 128677191 128677190 -1 -0.00% > sim_ops 248045844 248045840 -4 -0.00% > sim_ticks 5184749789500 5184749789500 0 > +0.00% > system.cpu.committedInsts 128677191 128677190 -1 -0.00% > system.cpu.committedOps 248045844 248045840 -4 -0.00% > > Differences > 0%: > > system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 0.075038 > 0.000001 +0.00% > system.cpu.dcache.overall_miss_rate::total 0.075037 0.075038 0.000001 > +0.00% > system.physmem_0.memoryStateTime::ACT 31977108390 31977112390 4000 > +0.00% > system.cpu.dcache.WriteReq_hits::cpu.data 8077139 8077138 -1 > -0.00% > system.cpu.dcache.WriteReq_hits::total 8077139 8077138 -1 > -0.00% > system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 8401893 > -1 -0.00% > system.cpu.dcache.WriteReq_accesses::total 8401894 8401893 -1 > -0.00% > system.cpu.num_store_insts 8409880 8409879 -1 -0.00% > system.cpu.op_class::MemWrite 8409880.000 8409879.000 -1.000 -0.00% > system.cpu.dcache.demand_hits::cpu.data 20092012 20092010 -2 > -0.00% > system.cpu.dcache.demand_hits::total 20092012 20092010 -2 > -0.00% > system.cpu.dcache.overall_hits::cpu.data 20150865 20150863 -2 > -0.00% > system.cpu.dcache.overall_hits::total 20150865 20150863 -2 > -0.00% > system.cpu.dcache.tags.total_refs 20153045 20153043 -2 -0.00% > system.cpu.dcache.demand_accesses::cpu.data 21323588 21323586 > -2 -0.00% > system.cpu.dcache.demand_accesses::total 21323588 21323586 -2 > -0.00% > system.cpu.dcache.overall_accesses::cpu.data 21785602 21785600 > -2 -0.00% > system.cpu.dcache.overall_accesses::total 21785602 21785600 -2 > -0.00% > system.cpu.dcache.tags.data_accesses 88765477 88765469 -8 > -0.00% > system.cpu.dcache.tags.tag_accesses 88765477 88765469 -8 > -0.00% > [... showing top 20 errors only, additional errors omitted ...] > > > Thanks, > > Nikos Nikoleris > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
