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Review request for Default. Repository: gem5 Description ------- Changeset 10787:7e7e473aa414 --------------------------- arm: Relax ordering for some uncacheable accesses We currently assume that all uncacheable memory accesses are strictly ordered. Instead of always enforcing strict ordering, we now only enforce it if the required memory type is device memory or strongly ordered memory. Diffs ----- src/arch/arm/tlb.cc 8a7285d6197e Diff: http://reviews.gem5.org/r/2721/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
