----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2716/#review5989 -----------------------------------------------------------
Are these the only two ISAs that should be changed? Why not the others? Also, it might be worth mentioning in the commit message that it would be easy enough to add snooping back in for a particular TLB design if it were ever actually needed. Just further justification for why this change makes sense. - Steve Reinhardt On March 30, 2015, 2:17 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2716/ > ----------------------------------------------------------- > > (Updated March 30, 2015, 2:17 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10782:a138e84cc998 > --------------------------- > arch, cpu: Do not forward snoops to table walker > > This patch simplifies the overall CPU by changing the TLB caches such > that they do not forward snoops to the table walker port(s). > > There is no reason for the ports to snoop as they do not actually take > any action, and from a performance point of view we are better of not > snooping more than we have to. > > > Diffs > ----- > > configs/common/O3_ARM_v7a.py 8a7285d6197e > src/arch/arm/stage2_mmu.hh 8a7285d6197e > src/arch/x86/pagetable_walker.hh 8a7285d6197e > configs/common/Caches.py 8a7285d6197e > > Diff: http://reviews.gem5.org/r/2716/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
