Hi Lokesh,

gem5 does indeed currently only capture the delay in the transition, and
still “clocks” the components that are affected. A more detailed model of
the PMIC and voltage regulators, battery etc can definitely be added, the
transitions refined etc. The question is how much it matters, and what
your ultimate goal is.

Based on the academic work I’ve seen done on DVFS I’d say there are far
more serious shortcomings to be addressed (e.g. Ignoring the OS).

Andreas

On 16/04/2015 16:28, "Lokesh Jindal" <[email protected]> wrote:

>Hello everyone
>
>In DVFS in real systems, there are 2 parameters that come into picture
>during voltage-frequency transition.
>1. "Core dead time" during which core does not execute anything and is
>the time taken to actually change the frequency.
>2. "voltage change time" during which the core is executing instructions.
>
>I have done some quick digging into the DVFS implementation in gem5. It
>seems there is one parameter "transition_latency" associated with dvfs
>handler. When a perlevel (V,f) change request is initiated, the handler
>schedules an event that changes the perflevel (V,F) after
>"transition_latency". I think this models only parameter (2) above
>(voltage change time) and the parameter (1) above (core dead time) is
>not modelled precisely.
>
>Please comment if this observation of mine seems accurate/inaccurate!
>
>--
>Regards
>Lokesh Jindal
>UW-Madison
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>http://m5sim.org/mailman/listinfo/gem5-dev


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