changeset a80d2d716a53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a80d2d716a53
description:
        stats: update a few stats from long O3 runs

        Very small changes to iew.predictedNotTakenIncorrect
        and iew.branchMispredicts.  Looks like similar updates
        were committed on April 3 (changeset 235ff1c046df), but
        only for the quick tests.

diffstat:

 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini          
    |  136 ++++++---
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr              
    |    3 +-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout              
    |   19 +-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt           
    |   14 +-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal     
    |  Bin 
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini  
    |   59 ++-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr      
    |  113 +++++++-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout      
    |   15 +-
 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt   
    |   16 +-
 
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
 |  Bin 
 tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini              
    |   32 +-
 tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout                  
    |   13 +-
 tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt               
    |   14 +-
 
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal 
   |    4 +-
 14 files changed, 290 insertions(+), 148 deletions(-)

diffs (truncated from 1152 to 300 lines):

diff -r 378b344385a8 -r a80d2d716a53 
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini     
Mon Apr 20 12:46:35 2015 -0400
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini     
Mon Apr 20 15:09:43 2015 -0700
@@ -12,12 +12,12 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl 
iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 
voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 
norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,21 @@
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +87,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -189,7 +190,7 @@
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.branchPred]
-type=BranchPredictor
+type=BiModeBP
 BTBEntries=2048
 BTBTagSize=18
 RASSize=16
@@ -199,11 +200,7 @@
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
 numThreads=1
-predType=bi-mode
 
 [system.cpu0.dcache]
 type=BaseCache
@@ -211,6 +208,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -245,6 +243,7 @@
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -262,7 +261,6 @@
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -552,8 +550,9 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
 is_top_level=true
 max_miss_count=0
@@ -620,6 +619,7 @@
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -637,7 +637,6 @@
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -662,6 +661,7 @@
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -683,19 +683,27 @@
 
 [system.cpu0.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu0.l2cache.tags]
@@ -712,13 +720,16 @@
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side 
system.cpu0.itb.walker.port system.cpu0.dtb.walker.port 
system.cpu0.istage2_mmu.stage2_tlb.walker.port 
system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side 
system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -816,7 +827,7 @@
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.branchPred]
-type=BranchPredictor
+type=BiModeBP
 BTBEntries=2048
 BTBTagSize=18
 RASSize=16
@@ -826,11 +837,7 @@
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
 numThreads=1
-predType=bi-mode
 
 [system.cpu1.dcache]
 type=BaseCache
@@ -838,6 +845,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -872,6 +880,7 @@
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -889,7 +898,6 @@
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -1179,8 +1187,9 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
 is_top_level=true
 max_miss_count=0
@@ -1247,6 +1256,7 @@
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -1264,7 +1274,6 @@
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -1289,6 +1298,7 @@
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -1310,19 +1320,27 @@
 
 [system.cpu1.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
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