> On April 29, 2015, 6:03 a.m., Amin Farmahini wrote: > > src/mem/DRAMCtrl.py, line 385 > > <http://reviews.gem5.org/r/2750/diff/1/?file=44803#file44803line385> > > > > Did you mean 4GB? HMC v2 defines 4GB and 8GB devices. or may be you > > mean 4Gb per layer and a total size of 2GB? or just an array? > > omar naji wrote: > 4Gb per layer and a total size of 2 GB
Perhaps add this more elaborate comment to avoid confusion? > On April 29, 2015, 6:03 a.m., Amin Farmahini wrote: > > src/mem/DRAMCtrl.py, line 417 > > <http://reviews.gem5.org/r/2750/diff/1/?file=44803#file44803line417> > > > > 16 banks per vault. Am I missing something? > > Can we not involve "layer" here? I mean it would be great if we could > > just abstract away layers in these parameters. > > omar naji wrote: > could you please elaborate more your question? I think it just needs a comment stating that each layer constitutes a rank, and with 16 banks overall, that leaves 2 banks per rank (for the configuration you have captured) etc - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2750/#review6093 ----------------------------------------------------------- On April 29, 2015, 6:14 p.m., omar naji wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2750/ > ----------------------------------------------------------- > > (Updated April 29, 2015, 6:14 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > A single HMC-2500 x32 model based on: > [1] DRAMSpec: a high-level DRAM bank modelling tool > developed at the University of Kaiserslautern. This high level tool > uses RC (resistance-capacitance) and CV (capacitance-voltage) models to > estimate the DRAM bank latency and power numbers. > [2] A Logic-base Interconnect for Supporting Near Memory Computation in the > Hybrid Memory Cube (E. Azarkhish et. al) > Assumed for the HMC model is a 30 nm technology node. > The modelled HMC consists of a 4 Gbit part with 4 layers connected with > TSVs. Each layer has 16 vaults and each vault consists of 2 banks per layer. > In order to be able to use the same controller used for 2D DRAM generations > for HMC, the following analogy is done: > Channel (DDR) => Vault (HMC) > device_size (DDR) => size of a single layer in a vault > ranks per channel (DDR) => number of layers > banks per rank (DDR) => banks per layer > devices per rank (DDR) => devices per layer ( 1 for HMC). > The parameters for which no input is available are inherited from the DDR3 > configuration. > > > Diffs > ----- > > src/mem/DRAMCtrl.py UNKNOWN > > Diff: http://reviews.gem5.org/r/2750/diff/ > > > Testing > ------- > > gem5 compiles. sweep.py runs > > > Thanks, > > omar naji > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
