changeset b9410e821c41 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b9410e821c41
description:
cpu: o3: single cycle default div microop latency on x86
This patch sets the default latency of the division microop to a single
cycle
on x86. This is because the division instructions DIV and IDIV have
been
implemented as loops of div microops, where each microop computes a
single bit
of the quotient.
diffstat:
src/cpu/o3/FuncUnitConfig.py | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diffs (27 lines):
diff -r f2c472d4ff9c -r b9410e821c41 src/cpu/o3/FuncUnitConfig.py
--- a/src/cpu/o3/FuncUnitConfig.py Wed Apr 29 22:35:22 2015 -0500
+++ b/src/cpu/o3/FuncUnitConfig.py Wed Apr 29 22:35:22 2015 -0500
@@ -39,6 +39,7 @@
# Authors: Kevin Lim
from m5.SimObject import SimObject
+from m5.defines import buildEnv
from m5.params import *
from FuncUnit import *
@@ -49,6 +50,15 @@
class IntMultDiv(FUDesc):
opList = [ OpDesc(opClass='IntMult', opLat=3),
OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+
+ # DIV and IDIV instructions in x86 are implemented using a loop which
+ # issues division microops. The latency of these microops should really be
+ # one (or a small number) cycle each since each of these computes one bit
+ # of the quotient.
+ if buildEnv['TARGET_ISA'] in ('x86'):
+ opList[1].opLat=1
+ opList[1].issueLat=1
+
count=2
class FP_ALU(FUDesc):
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
