changeset 64cd1dcd61a5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=64cd1dcd61a5
description:
mem, alpha: Move Alpha-specific request flags
Move Alpha-specific memory request flags to an architecture-specific
header and map them to the architecture specific flag bit range.
diffstat:
src/arch/alpha/faults.cc | 2 +-
src/arch/alpha/isa/pal.isa | 4 ++--
src/arch/alpha/tlb.cc | 4 ++--
src/arch/alpha/types.hh | 16 ++++++++++++++++
src/mem/request.hh | 4 ----
5 files changed, 21 insertions(+), 9 deletions(-)
diffs (87 lines):
diff -r d259f2bc2b31 -r 64cd1dcd61a5 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Tue May 05 03:22:30 2015 -0400
+++ b/src/arch/alpha/faults.cc Tue May 05 03:22:31 2015 -0400
@@ -147,7 +147,7 @@
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
- if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
diff -r d259f2bc2b31 -r 64cd1dcd61a5 src/arch/alpha/isa/pal.isa
--- a/src/arch/alpha/isa/pal.isa Tue May 05 03:22:30 2015 -0400
+++ b/src/arch/alpha/isa/pal.isa Tue May 05 03:22:31 2015 -0400
@@ -171,8 +171,8 @@
{
memAccessFlags.clear();
if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
- if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
- if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
+ if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE);
+ if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
}
diff -r d259f2bc2b31 -r 64cd1dcd61a5 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Tue May 05 03:22:30 2015 -0400
+++ b/src/arch/alpha/tlb.cc Tue May 05 03:22:31 2015 -0400
@@ -466,7 +466,7 @@
}
if (PcPAL(req->getPC())) {
- mode = (req->getFlags() & Request::ALTMODE) ?
+ mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
(mode_type)ALT_MODE_AM(
tc->readMiscRegNoEffect(IPR_ALT_MODE))
: mode_kernel;
@@ -523,7 +523,7 @@
if (write) { write_misses++; } else { read_misses++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK;
- return (req->getFlags() & Request::VPTE) ?
+ return (req->getFlags() & AlphaRequestFlags::VPTE) ?
(Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
req->getFlags(),
flags)) :
diff -r d259f2bc2b31 -r 64cd1dcd61a5 src/arch/alpha/types.hh
--- a/src/arch/alpha/types.hh Tue May 05 03:22:30 2015 -0400
+++ b/src/arch/alpha/types.hh Tue May 05 03:22:31 2015 -0400
@@ -51,6 +51,22 @@
ITOUCH_ANNOTE = 0xffffffff
};
+/**
+ * Alpha-specific memory request flags
+ *
+ * These flags map to the architecture-specific lower 8 bits of the
+ * flags field in Request.
+ */
+struct AlphaRequestFlags
+{
+ typedef uint8_t ArchFlagsType;
+
+ /** The request is an ALPHA VPTE pal access (hw_ld). */
+ static const ArchFlagsType VPTE = 0x01;
+ /** Use the alternate mode bits in ALPHA. */
+ static const ArchFlagsType ALTMODE = 0x02;
+};
+
} // namespace AlphaISA
#endif // __ARCH_ALPHA_TYPES_HH__
diff -r d259f2bc2b31 -r 64cd1dcd61a5 src/mem/request.hh
--- a/src/mem/request.hh Tue May 05 03:22:30 2015 -0400
+++ b/src/mem/request.hh Tue May 05 03:22:31 2015 -0400
@@ -101,10 +101,6 @@
static const FlagsType INST_FETCH = 0x00000100;
/** The virtual address is also the physical address. */
static const FlagsType PHYSICAL = 0x00000200;
- /** The request is an ALPHA VPTE pal access (hw_ld). */
- static const FlagsType VPTE = 0x00000400;
- /** Use the alternate mode bits in ALPHA. */
- static const FlagsType ALTMODE = 0x00000800;
/** The request is to an uncacheable address. */
static const FlagsType UNCACHEABLE = 0x00001000;
/** This request is to a memory mapped register. */
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