changeset 5d059b8ed8a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5d059b8ed8a4
description:
arm: Relax ordering for some uncacheable accesses
We currently assume that all uncacheable memory accesses are strictly
ordered. Instead of always enforcing strict ordering, we now only
enforce it if the required memory type is device memory or strongly
ordered memory.
diffstat:
src/arch/arm/tlb.cc | 8 +++++++-
1 files changed, 7 insertions(+), 1 deletions(-)
diffs (18 lines):
diff -r 308771bd2647 -r 5d059b8ed8a4 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Tue May 05 03:22:33 2015 -0400
+++ b/src/arch/arm/tlb.cc Tue May 05 03:22:34 2015 -0400
@@ -1076,7 +1076,13 @@
setAttr(te->attributes);
if (te->nonCacheable)
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
+ req->setFlags(Request::UNCACHEABLE);
+
+ // Require requests to be ordered if the request goes to
+ // strongly ordered or device memory (i.e., anything other
+ // than normal memory requires strict order).
+ if (te->mtype != TlbEntry::MemoryType::Normal)
+ req->setFlags(Request::STRICT_ORDER);
Addr pa = te->pAddr(vaddr);
req->setPaddr(pa);
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
