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Review request for Default. Repository: gem5 Description ------- Changeset 10841:b015addd7b9d --------------------------- mem: MSHR livelock bug fix This patch was created by Bihn Pham during his internship at AMD. This bug fix prevents a case in which a prefetcher uses up all remaining MSHR entries before demand requests get a chance to, causing a livelock. This happens because events scheduled at curTick() + 1 are evaluated in the next cycle, not in the current cycle. A specific case that caused this livelock situation is the following: There are back-to-back stores and the second store cannot be sent to the cache until the first store receives an ACK. When the ACK is scheduled at curTick() + 1, meaning that the ACK is to be sent in the next cycle, there is an open MSHR entry in the current cycle. A prefetcher grabs the entry by issuing a prefetch request in the current cycle before the second store gets a chance to issue in the next cycle. The second store stalls because the MSHR is already full by that time. Diffs ----- src/mem/packet_queue.cc fbdaa08aaa426b9f4660c366f934ccb670d954ec Diff: http://reviews.gem5.org/r/2784/diff/ Testing ------- Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
