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Can you comment on how this affects statistics? Seems likely to be minor, but for instance, 1 cycle can be huge when sequencing CPU L1 hits. - Joel Hestness On May 11, 2015, 10:19 p.m., Tony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2785/ > ----------------------------------------------------------- > > (Updated May 11, 2015, 10:19 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10842:eea05dd8ca10 > --------------------------- > mem: Hit callback delay fix > > This patch was created by Bihn Pham during his internship at AMD. > > There is no need to delay hit callback response messages by a cycle because > the response latency is already incurred in the Ruby protocol. This ensures > correct timing of memory instructions. > > > Diffs > ----- > > src/mem/ruby/system/RubyPort.cc fbdaa08aaa426b9f4660c366f934ccb670d954ec > > Diff: http://reviews.gem5.org/r/2785/diff/ > > > Testing > ------- > > > Thanks, > > Tony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
