changeset f7a36ade78c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f7a36ade78c2
description:
sim: Don't clear the active CPU vector in System::initState
The system class currently clears the vector of active CPUs in
initState(). CPUs are added to the list by registerThreadContext()
which is called from BaseCPU::init(). This obviously breaks when the
System object is initialized after the CPUs. This changeset removes
the offending clear() call since the list will be empty after it has
been instantiated anyway.
diffstat:
src/sim/system.cc | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diffs (12 lines):
diff -r a4a2ba97a654 -r f7a36ade78c2 src/sim/system.cc
--- a/src/sim/system.cc Fri May 15 13:38:46 2015 -0400
+++ b/src/sim/system.cc Fri May 15 13:39:44 2015 -0400
@@ -302,8 +302,6 @@
DPRINTF(Loader, "Kernel loaded...\n");
}
}
-
- activeCpus.clear();
}
void
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
