changeset d4b162a57400 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d4b162a57400
description:
misc: Appease gcc 5.1
Three minor issues are resolved:
1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.
2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.
3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
diffstat:
src/arch/x86/insts/microop.cc | 8 ++++----
src/arch/x86/isa_traits.hh | 2 +-
src/cpu/base_dyn_inst.hh | 9 +++++----
src/cpu/o3/dyn_inst.hh | 6 ++++--
4 files changed, 14 insertions(+), 11 deletions(-)
diffs (117 lines):
diff -r f7a36ade78c2 -r d4b162a57400 src/arch/x86/insts/microop.cc
--- a/src/arch/x86/insts/microop.cc Fri May 15 13:39:44 2015 -0400
+++ b/src/arch/x86/insts/microop.cc Fri May 15 13:39:53 2015 -0400
@@ -55,7 +55,7 @@
case ConditionTests::EZF:
return ccflags.ezf;
case ConditionTests::SZnZF:
- return !(!ccflags.ezf & ccflags.zf);
+ return !(!ccflags.ezf && ccflags.zf);
case ConditionTests::MSTRZ:
panic("This condition is not implemented!");
case ConditionTests::STRZ:
@@ -63,7 +63,7 @@
case ConditionTests::MSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRZnEZF:
- return !ccflags.ezf & ccflags.zf;
+ return !ccflags.ezf && ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::OF:
return ccflags.of;
@@ -88,7 +88,7 @@
case ConditionTests::NotEZF:
return !ccflags.ezf;
case ConditionTests::NotSZnZF:
- return !ccflags.ezf & ccflags.zf;
+ return !ccflags.ezf && ccflags.zf;
case ConditionTests::NotMSTRZ:
panic("This condition is not implemented!");
case ConditionTests::NotSTRZ:
@@ -96,7 +96,7 @@
case ConditionTests::NotMSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRnZnEZF:
- return !ccflags.ezf & !ccflags.zf;
+ return !ccflags.ezf && !ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::NotOF:
return !ccflags.of;
diff -r f7a36ade78c2 -r d4b162a57400 src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh Fri May 15 13:39:44 2015 -0400
+++ b/src/arch/x86/isa_traits.hh Fri May 15 13:39:53 2015 -0400
@@ -68,7 +68,7 @@
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
- const ExtMachInst NoopMachInst = {
+ const ExtMachInst NoopMachInst M5_VAR_USED = {
0x0, // No legacy prefixes.
0x0, // No rex prefix.
{ OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
diff -r f7a36ade78c2 -r d4b162a57400 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Fri May 15 13:39:44 2015 -0400
+++ b/src/cpu/base_dyn_inst.hh Fri May 15 13:39:53 2015 -0400
@@ -46,6 +46,7 @@
#ifndef __CPU_BASE_DYN_INST_HH__
#define __CPU_BASE_DYN_INST_HH__
+#include <array>
#include <bitset>
#include <list>
#include <string>
@@ -258,22 +259,22 @@
/** Flattened register index of the destination registers of this
* instruction.
*/
- TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
+ std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx;
/** Physical register index of the destination registers of this
* instruction.
*/
- PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
+ std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx;
/** Physical register index of the source registers of this
* instruction.
*/
- PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
+ std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx;
/** Physical register index of the previous producers of the
* architected destinations.
*/
- PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
+ std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx;
public:
diff -r f7a36ade78c2 -r d4b162a57400 src/cpu/o3/dyn_inst.hh
--- a/src/cpu/o3/dyn_inst.hh Fri May 15 13:39:44 2015 -0400
+++ b/src/cpu/o3/dyn_inst.hh Fri May 15 13:39:53 2015 -0400
@@ -44,6 +44,8 @@
#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__
+#include <array>
+
#include "arch/isa_traits.hh"
#include "config/the_isa.hh"
#include "cpu/o3/cpu.hh"
@@ -108,13 +110,13 @@
protected:
/** Values to be written to the destination misc. registers. */
- MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
+ std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to defer
* the write accesses to the misc. registers until the commit stage, when
* the instruction is out of its speculative state.
*/
- short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
+ std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
/** Number of destination misc. registers. */
uint8_t _numDestMiscRegs;
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