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Review request for Default. Repository: gem5 Description ------- Changeset 10840:3276d40bc0e1 --------------------------- x86: changes to emulenv for instructions with vex prefix A new register has been added since AVX instructions can have two source and a separate destination operand. Changes made to SIB byte can be read in manuals from AMD and Intel. Diffs ----- src/arch/x86/emulenv.hh 9b424e7adac5 src/arch/x86/emulenv.cc 9b424e7adac5 src/arch/x86/isa/macroop.isa 9b424e7adac5 src/arch/x86/isa/microops/base.isa 9b424e7adac5 Diff: http://reviews.gem5.org/r/2830/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
