On Mon, 18 May 2015, Brad Beckmann wrote:
On May 18, 2015, 10:06 p.m., Nilay Vaish wrote:
I have asked this question before when Steve posted this patch several months
ago.
I am going to ask it again? Is it all right to buffer requests in the
Sequencer?
Do we know of CPU designs that do so? What problems do we face when we push
through
requests for same address to the cache controllers?
Yes, it is ok to buffer requests in the Sequencer. We are pretty
satisfied with the correlation results against our hardware using Ruby.
The Sequencer is a simplification of much more complicated buffering in
real hardware. That simplification is a very good thing.
I need some reference on this. I talked to Prof. Wood about it and he
said that he is not aware of any CPUs that do this.
I believe it is pretty universal across most designs that they don't
allow a single CPU to issue multiple requests for the same cache line
that go out throughout the memory system. That has huge power and
complexity implications.
Note that the L0/L1 controller would serve those requests from the same
cache block. So requests would not be sent out beyond the L0/L1
controller. And as much as I understand the protocols currently in gem5,
if we completely remove the aliasing support from sequencer, the L0/L1
controllers would either merge or block aliased requests.
--
Nilay
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