----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2762/#review6355 -----------------------------------------------------------
src/dev/arm/generic_timer.hh (line 70) <http://reviews.gem5.org/r/2762/#comment5478> Would it be possible to change the name to something a bit simpler? Now I see where GIC can be useful, neat\! - Alexandru Dutu On May 7, 2015, 10:59 a.m., Andreas Sandberg wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2762/ > ----------------------------------------------------------- > > (Updated May 7, 2015, 10:59 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10839:97a0dceec537 > --------------------------- > dev, arm: Refactor and clean up the generic timer model > > This changeset cleans up the generic timer a bit and moves most of the > register juggling from the ISA code into a separate class in the same > source file as the rest of the generic timer. It also removes the > assumption that there is always 8 or fewer CPUs in the system. Instead > of having a fixed limit, we now instantiate per-core timers as they > are requested. This is all in preparation for other patches that add > support for virtual timers and a memory mapped interface. > > > Diffs > ----- > > src/arch/arm/isa.hh fbdaa08aaa42 > src/arch/arm/isa.cc fbdaa08aaa42 > src/arch/arm/system.hh fbdaa08aaa42 > src/arch/arm/system.cc fbdaa08aaa42 > src/dev/arm/RealView.py fbdaa08aaa42 > src/dev/arm/generic_timer.hh fbdaa08aaa42 > src/dev/arm/generic_timer.cc fbdaa08aaa42 > > Diff: http://reviews.gem5.org/r/2762/diff/ > > > Testing > ------- > > ARM regressions pass. All backends build. > > > Thanks, > > Andreas Sandberg > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
