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Review request for Default. Repository: gem5 Description ------- Changeset 10838:baafddd2a2d6 --------------------------- ruby: Fix MESI consistency bug Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load reordering, as the LQ is never notified of the invalidate. Diffs ----- src/mem/protocol/MESI_Two_Level-L1cache.sm ecbab2522757 Diff: http://reviews.gem5.org/r/2840/diff/ Testing ------- Tester no longer finds memory consistency violation. Thanks, Marco Elver _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
