changeset f449d6f8a647 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f449d6f8a647
description:
arm: Make address translation faster with better caching
This patch adds better caching of the sys regs for AArch64, thus
avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the
non-faulting case.
diffstat:
src/arch/arm/tlb.cc | 11 +++++------
src/arch/arm/tlb.hh | 1 +
src/arch/arm/utility.cc | 32 ++++++++++++++++++++++++++++++++
src/arch/arm/utility.hh | 2 ++
4 files changed, 40 insertions(+), 6 deletions(-)
diffs (121 lines):
diff -r 5312e4cb6547 -r f449d6f8a647 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Tue May 26 03:21:40 2015 -0400
+++ b/src/arch/arm/tlb.cc Tue May 26 03:21:42 2015 -0400
@@ -546,7 +546,7 @@
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = 0;
if (aarch64)
- vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
+ vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
uint32_t flags = req->getFlags();
@@ -765,7 +765,7 @@
assert(aarch64);
Addr vaddr_tainted = req->getVaddr();
- Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
+ Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
uint32_t flags = req->getFlags();
bool is_fetch = (mode == Execute);
@@ -959,7 +959,7 @@
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = 0;
if (aarch64)
- vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
+ vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
uint32_t flags = req->getFlags();
@@ -1110,7 +1110,6 @@
// Generate Illegal Inst Set State fault if IL bit is set in CPSR
if (fault == NoFault) {
- CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
if (aarch64 && is_fetch && cpsr.il == 1) {
return std::make_shared<IllegalInstSetStateFault>();
}
@@ -1222,7 +1221,7 @@
}
DPRINTF(TLBVerbose, "TLB variables changed!\n");
- CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+ cpsr = tc->readMiscReg(MISCREG_CPSR);
// Dependencies: SCR/SCR_EL3, CPSR
isSecure = inSecureState(tc);
isSecure &= (tranType & HypMode) == 0;
@@ -1328,7 +1327,7 @@
Addr vaddr = 0;
ExceptionLevel target_el = aarch64 ? aarch64EL : EL1;
if (aarch64) {
- vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el);
+ vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr);
} else {
vaddr = vaddr_tainted;
}
diff -r 5312e4cb6547 -r f449d6f8a647 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Tue May 26 03:21:40 2015 -0400
+++ b/src/arch/arm/tlb.hh Tue May 26 03:21:42 2015 -0400
@@ -312,6 +312,7 @@
// translateFunctional/translateSe/translateFs checks if they are
// invalid and call updateMiscReg if necessary.
protected:
+ CPSR cpsr;
bool aarch64;
ExceptionLevel aarch64EL;
SCTLR sctlr;
diff -r 5312e4cb6547 -r f449d6f8a647 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Tue May 26 03:21:40 2015 -0400
+++ b/src/arch/arm/utility.cc Tue May 26 03:21:42 2015 -0400
@@ -272,6 +272,38 @@
}
Addr
+purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
+ TTBCR tcr)
+{
+ switch (el) {
+ case EL0:
+ case EL1:
+ if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
+ return addr | mask(63, 55);
+ else if (!bits(addr, 55, 48) && tcr.tbi0)
+ return bits(addr,55, 0);
+ break;
+ // @todo: uncomment this to enable Virtualization
+ // case EL2:
+ // assert(ArmSystem::haveVirtualization());
+ // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
+ // if (tcr.tbi)
+ // return addr & mask(56);
+ // break;
+ case EL3:
+ assert(ArmSystem::haveSecurity(tc));
+ if (tcr.tbi)
+ return addr & mask(56);
+ break;
+ default:
+ panic("Invalid exception level");
+ break;
+ }
+
+ return addr; // Nothing to do if this is not a tagged address
+}
+
+Addr
purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
{
TTBCR tcr;
diff -r 5312e4cb6547 -r f449d6f8a647 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Tue May 26 03:21:40 2015 -0400
+++ b/src/arch/arm/utility.hh Tue May 26 03:21:42 2015 -0400
@@ -168,6 +168,8 @@
* @param el The controlled exception level.
* @return The purified address.
*/
+Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
+ TTBCR tcr);
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
static inline bool
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