----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2828/ -----------------------------------------------------------
(Updated May 27, 2015, 10:29 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10850:ecb65c144bbf --------------------------- cpu: implements vector registers This patch aims at adding vector registers type. The type is defined as a std::array of some fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now. Diffs (updated) ----- src/arch/SConscript e61f847e74fd src/arch/alpha/registers.hh e61f847e74fd src/arch/arm/registers.hh e61f847e74fd src/arch/isa_parser.py e61f847e74fd src/arch/mips/registers.hh e61f847e74fd src/arch/null/registers.hh e61f847e74fd src/arch/power/registers.hh e61f847e74fd src/arch/sparc/registers.hh e61f847e74fd src/arch/x86/insts/static_inst.cc e61f847e74fd src/arch/x86/isa.hh e61f847e74fd src/arch/x86/registers.hh e61f847e74fd src/cpu/StaticInstFlags.py e61f847e74fd src/cpu/base_dyn_inst.hh e61f847e74fd src/cpu/checker/cpu.hh e61f847e74fd src/cpu/checker/cpu_impl.hh e61f847e74fd src/cpu/checker/thread_context.hh e61f847e74fd src/cpu/exec_context.hh e61f847e74fd src/cpu/o3/O3CPU.py e61f847e74fd src/cpu/o3/cpu.hh e61f847e74fd src/cpu/o3/cpu.cc e61f847e74fd src/cpu/o3/dyn_inst.hh e61f847e74fd src/cpu/o3/free_list.hh e61f847e74fd src/cpu/o3/regfile.hh e61f847e74fd src/cpu/o3/regfile.cc e61f847e74fd src/cpu/o3/rename_map.hh e61f847e74fd src/cpu/o3/thread_context.hh e61f847e74fd src/cpu/o3/thread_context_impl.hh e61f847e74fd src/cpu/reg_class.hh e61f847e74fd src/cpu/simple/base.hh e61f847e74fd src/cpu/simple_thread.hh e61f847e74fd src/cpu/static_inst.hh e61f847e74fd src/cpu/thread_context.hh e61f847e74fd src/sim/insttracer.hh e61f847e74fd Diff: http://reviews.gem5.org/r/2828/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
