changeset 282c2a89ace8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=282c2a89ace8
description:
ruby: Fix MESI consistency bug
Fixes missed forward eviction to CPU. With the O3CPU this can lead to
load-load
reordering, as the LQ is never notified of the invalidate.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/mem/protocol/MESI_Two_Level-L1cache.sm | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (11 lines):
diff -r 83cec4049505 -r 282c2a89ace8 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Sun Jun 07 14:02:40
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Sun Jun 07 14:02:40
2015 -0500
@@ -1341,6 +1341,7 @@
// transitions from SM
transition(SM, Inv, IM) {
+ forward_eviction_to_cpu;
fi_sendInvAck;
dg_invalidate_sc;
l_popRequestQueue;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
