----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2851/#review6486 -----------------------------------------------------------
src/cpu/o3/cpu.cc (line 295) <http://reviews.gem5.org/r/2851/#comment5565> Initially, physical register are assigned consecutively to architectural register. We want to have just one physical register for all hardware threads. It seems that moving this outside the loop will accomplish the same behavior. src/cpu/o3/cpu.cc (line 300) <http://reviews.gem5.org/r/2851/#comment5566> This does not take care of different threads. - Alexandru Dutu On May 28, 2015, 3:38 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2851/ > ----------------------------------------------------------- > > (Updated May 28, 2015, 3:38 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10859:9c783a1367cd > --------------------------- > cpu: o3: Mapping the ZeroRegister for all hardware threads > This patch helps enabling SMT in x86 by mapping the ZeroRegister to one > physical register across all hardware threads. > > > Diffs > ----- > > src/cpu/o3/cpu.cc d02b45a554b52c68cce41e1b3895fb8582a639dd > > Diff: http://reviews.gem5.org/r/2851/diff/ > > > Testing > ------- > > Quick regressions passed for all ISAs. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
