changeset a6ca6831e775 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a6ca6831e775
description:
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.
* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).
* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.
* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
diffstat:
src/arch/alpha/interrupts.hh | 4 +-
src/arch/alpha/isa.cc | 4 +-
src/arch/alpha/isa.hh | 4 +-
src/arch/alpha/kernel_stats.cc | 8 +-
src/arch/alpha/kernel_stats.hh | 4 +-
src/arch/alpha/pagetable.cc | 4 +-
src/arch/alpha/pagetable.hh | 11 +-
src/arch/alpha/process.cc | 2 +-
src/arch/alpha/process.hh | 2 +-
src/arch/alpha/system.cc | 12 +-
src/arch/alpha/system.hh | 4 +-
src/arch/alpha/tlb.cc | 27 +-
src/arch/alpha/tlb.hh | 11 +-
src/arch/arm/interrupts.hh | 4 +-
src/arch/arm/isa.hh | 4 +-
src/arch/arm/kvm/gic.cc | 4 +-
src/arch/arm/kvm/gic.hh | 2 +-
src/arch/arm/pagetable.hh | 14 +-
src/arch/arm/pmu.cc | 21 +-
src/arch/arm/pmu.hh | 10 +-
src/arch/arm/tlb.cc | 15 +-
src/arch/arm/tlb.hh | 4 +-
src/arch/arm/types.hh | 8 +-
src/arch/generic/types.hh | 30 +-
src/arch/mips/interrupts.hh | 4 +-
src/arch/mips/pagetable.cc | 4 +-
src/arch/mips/pagetable.hh | 8 +-
src/arch/mips/tlb.cc | 11 +-
src/arch/mips/tlb.hh | 4 +-
src/arch/power/pagetable.cc | 4 +-
src/arch/power/pagetable.hh | 5 +-
src/arch/power/tlb.cc | 10 +-
src/arch/power/tlb.hh | 9 +-
src/arch/sparc/interrupts.hh | 4 +-
src/arch/sparc/isa.cc | 4 +-
src/arch/sparc/isa.hh | 5 +-
src/arch/sparc/pagetable.cc | 4 +-
src/arch/sparc/pagetable.hh | 4 +-
src/arch/sparc/system.cc | 28 +-
src/arch/sparc/system.hh | 4 +-
src/arch/sparc/tlb.cc | 39 +--
src/arch/sparc/tlb.hh | 4 +-
src/arch/x86/interrupts.cc | 4 +-
src/arch/x86/interrupts.hh | 5 +-
src/arch/x86/isa.cc | 4 +-
src/arch/x86/isa.hh | 5 +-
src/arch/x86/pagetable.cc | 13 +-
src/arch/x86/pagetable.hh | 8 +-
src/arch/x86/tlb.cc | 21 +-
src/arch/x86/tlb.hh | 6 +-
src/arch/x86/types.cc | 57 ++---
src/arch/x86/types.hh | 14 +-
src/base/cp_annotate.cc | 97 ++++-----
src/base/cp_annotate.hh | 12 +-
src/base/loader/symtab.cc | 17 +-
src/base/loader/symtab.hh | 7 +-
src/base/pollevent.cc | 4 +-
src/base/pollevent.hh | 6 +-
src/base/random.cc | 8 +-
src/base/random.hh | 8 +-
src/base/time.cc | 13 +-
src/base/time.hh | 8 +-
src/cpu/base.cc | 18 +-
src/cpu/base.hh | 9 +-
src/cpu/checker/cpu.cc | 4 +-
src/cpu/checker/cpu.hh | 4 +-
src/cpu/checker/thread_context.hh | 4 -
src/cpu/kvm/BaseKvmCPU.py | 2 +-
src/cpu/kvm/base.cc | 11 +-
src/cpu/kvm/base.hh | 9 +-
src/cpu/kvm/x86_cpu.cc | 2 +-
src/cpu/kvm/x86_cpu.hh | 2 +-
src/cpu/minor/cpu.cc | 21 +-
src/cpu/minor/cpu.hh | 10 +-
src/cpu/o3/cpu.cc | 9 +-
src/cpu/o3/cpu.hh | 7 +-
src/cpu/o3/thread_state.hh | 12 +-
src/cpu/simple/base.cc | 9 +-
src/cpu/simple/base.hh | 6 +-
src/cpu/simple_thread.cc | 12 +-
src/cpu/simple_thread.hh | 4 +-
src/cpu/testers/traffic_gen/traffic_gen.cc | 4 +-
src/cpu/testers/traffic_gen/traffic_gen.hh | 5 +-
src/cpu/thread_context.cc | 12 +-
src/cpu/thread_context.hh | 4 +-
src/cpu/thread_state.cc | 8 +-
src/cpu/thread_state.hh | 6 +-
src/dev/alpha/backdoor.cc | 12 +-
src/dev/alpha/backdoor.hh | 10 +-
src/dev/alpha/tsunami.cc | 4 +-
src/dev/alpha/tsunami.hh | 14 +-
src/dev/alpha/tsunami_cchip.cc | 4 +-
src/dev/alpha/tsunami_cchip.hh | 16 +-
src/dev/alpha/tsunami_io.cc | 12 +-
src/dev/alpha/tsunami_io.hh | 14 +-
src/dev/alpha/tsunami_pchip.cc | 4 +-
src/dev/alpha/tsunami_pchip.hh | 14 +-
src/dev/arm/energy_ctrl.cc | 4 +-
src/dev/arm/energy_ctrl.hh | 4 +-
src/dev/arm/flash_device.cc | 4 +-
src/dev/arm/flash_device.hh | 5 +-
src/dev/arm/generic_timer.cc | 62 ++---
src/dev/arm/generic_timer.hh | 20 +-
src/dev/arm/gic_pl390.cc | 4 +-
src/dev/arm/gic_pl390.hh | 4 +-
src/dev/arm/hdlcd.cc | 16 +-
src/dev/arm/hdlcd.hh | 4 +-
src/dev/arm/kmi.cc | 8 +-
src/dev/arm/kmi.hh | 4 +-
src/dev/arm/pl011.cc | 12 +-
src/dev/arm/pl011.hh | 4 +-
src/dev/arm/pl111.cc | 8 +-
src/dev/arm/pl111.hh | 4 +-
src/dev/arm/rtc_pl031.cc | 4 +-
src/dev/arm/rtc_pl031.hh | 5 +-
src/dev/arm/rv_ctrl.cc | 4 +-
src/dev/arm/rv_ctrl.hh | 5 +-
src/dev/arm/timer_cpulocal.cc | 19 +-
src/dev/arm/timer_cpulocal.hh | 11 +-
src/dev/arm/timer_sp804.cc | 18 +-
src/dev/arm/timer_sp804.hh | 11 +-
src/dev/arm/ufs_device.cc | 12 +-
src/dev/arm/ufs_device.hh | 4 +-
src/dev/arm/vgic.cc | 125 ++++++-------
src/dev/arm/vgic.hh | 25 ++-
src/dev/copy_engine.cc | 32 +-
src/dev/copy_engine.hh | 10 +-
src/dev/copy_engine_defs.hh | 36 +-
src/dev/disk_image.cc | 12 +-
src/dev/disk_image.hh | 9 +-
src/dev/etherlink.cc | 60 +++---
src/dev/etherlink.hh | 9 +-
src/dev/etherpkt.cc | 13 +-
src/dev/etherpkt.hh | 7 +-
src/dev/ethertap.cc | 8 +-
src/dev/ethertap.hh | 4 +-
src/dev/i2cbus.cc | 4 +-
src/dev/i2cbus.hh | 4 +-
src/dev/i8254xGBe.cc | 66 +++---
src/dev/i8254xGBe.hh | 21 +-
src/dev/i8254xGBe_defs.hh | 158 ++++++++--------
src/dev/ide_ctrl.cc | 62 +++---
src/dev/ide_ctrl.hh | 9 +-
src/dev/ide_disk.cc | 4 +-
src/dev/ide_disk.hh | 14 +-
src/dev/intel_8254_timer.cc | 58 ++---
src/dev/intel_8254_timer.hh | 10 +-
src/dev/mc146818.cc | 17 +-
src/dev/mc146818.hh | 5 +-
src/dev/mips/malta.cc | 4 +-
src/dev/mips/malta.hh | 14 +-
src/dev/mips/malta_cchip.cc | 4 +-
src/dev/mips/malta_cchip.hh | 16 +-
src/dev/mips/malta_io.cc | 12 +-
src/dev/mips/malta_io.hh | 14 +-
src/dev/mips/malta_pchip.cc | 4 +-
src/dev/mips/malta_pchip.hh | 14 +-
src/dev/ns_gige.cc | 24 +-
src/dev/ns_gige.hh | 4 +-
src/dev/pcidev.cc | 108 +++++-----
src/dev/pcidev.hh | 4 +-
src/dev/pktfifo.cc | 53 ++---
src/dev/pktfifo.hh | 10 +-
src/dev/sinic.cc | 78 ++++----
src/dev/sinic.hh | 8 +-
src/dev/sparc/dtod.cc | 4 +-
src/dev/sparc/dtod.hh | 16 +-
src/dev/sparc/iob.cc | 34 +-
src/dev/sparc/iob.hh | 5 +-
src/dev/sparc/mm_disk.cc | 2 +-
src/dev/sparc/mm_disk.hh | 2 +-
src/dev/uart8250.cc | 4 +-
src/dev/uart8250.hh | 5 +-
src/dev/virtio/base.cc | 24 +-
src/dev/virtio/base.hh | 13 +-
src/dev/virtio/fs9p.cc | 4 +-
src/dev/virtio/fs9p.hh | 4 +-
src/dev/x86/cmos.cc | 8 +-
src/dev/x86/cmos.hh | 4 +-
src/dev/x86/i8042.cc | 58 ++---
src/dev/x86/i8042.hh | 14 +-
src/dev/x86/i82094aa.cc | 4 +-
src/dev/x86/i82094aa.hh | 4 +-
src/dev/x86/i8237.cc | 4 +-
src/dev/x86/i8237.hh | 4 +-
src/dev/x86/i8254.cc | 8 +-
src/dev/x86/i8254.hh | 5 +-
src/dev/x86/i8259.cc | 4 +-
src/dev/x86/i8259.hh | 4 +-
src/dev/x86/speaker.cc | 4 +-
src/dev/x86/speaker.hh | 5 +-
src/kern/kernel_stats.cc | 4 +-
src/kern/kernel_stats.hh | 4 +-
src/mem/cache/cache.hh | 4 +-
src/mem/cache/cache_impl.hh | 4 +-
src/mem/multi_level_page_table.hh | 4 +-
src/mem/multi_level_page_table_impl.hh | 9 +-
src/mem/page_table.cc | 40 +--
src/mem/page_table.hh | 11 +-
src/mem/physical.cc | 29 +-
src/mem/physical.hh | 10 +-
src/mem/ruby/system/System.cc | 8 +-
src/mem/ruby/system/System.hh | 4 +-
src/python/m5/SimObject.py | 2 +-
src/python/swig/core.i | 4 +-
src/python/swig/pyobject.cc | 4 +-
src/python/swig/pyobject.hh | 4 +-
src/sim/clock_domain.cc | 8 +-
src/sim/clock_domain.hh | 5 +-
src/sim/cxx_manager.cc | 2 +-
src/sim/cxx_manager.hh | 4 +-
src/sim/dvfs_handler.cc | 23 +-
src/sim/dvfs_handler.hh | 4 +-
src/sim/eventq.cc | 21 +-
src/sim/eventq.hh | 11 +-
src/sim/process.cc | 25 +-
src/sim/process.hh | 12 +-
src/sim/root.cc | 6 +-
src/sim/root.hh | 7 +-
src/sim/serialize.cc | 274 ++++++++++++++++------------
src/sim/serialize.hh | 253 +++++++++++++++++++++-----
src/sim/sim_events.cc | 17 +-
src/sim/sim_events.hh | 10 +-
src/sim/sim_object.cc | 15 +-
src/sim/sim_object.hh | 8 +-
src/sim/system.cc | 17 +-
src/sim/system.hh | 9 +-
src/sim/ticked_object.cc | 20 +-
src/sim/ticked_object.hh | 10 +-
src/sim/voltage_domain.cc | 6 +-
src/sim/voltage_domain.hh | 5 +-
231 files changed, 1787 insertions(+), 1773 deletions(-)
diffs (truncated from 9173 to 300 lines):
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/interrupts.hh Tue Jul 07 09:51:03 2015 +0100
@@ -121,14 +121,14 @@
}
void
- serialize(std::ostream &os)
+ serialize(CheckpointOut &cp) const
{
SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
SERIALIZE_SCALAR(intstatus);
}
void
- unserialize(Checkpoint *cp, const std::string §ion)
+ unserialize(CheckpointIn &cp)
{
UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
UNSERIALIZE_SCALAR(intstatus);
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/isa.cc
--- a/src/arch/alpha/isa.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/isa.cc Tue Jul 07 09:51:03 2015 +0100
@@ -53,7 +53,7 @@
}
void
-ISA::serialize(std::ostream &os)
+ISA::serialize(CheckpointOut &cp) const
{
SERIALIZE_SCALAR(fpcr);
SERIALIZE_SCALAR(uniq);
@@ -63,7 +63,7 @@
}
void
-ISA::unserialize(Checkpoint *cp, const std::string §ion)
+ISA::unserialize(CheckpointIn &cp)
{
UNSERIALIZE_SCALAR(fpcr);
UNSERIALIZE_SCALAR(uniq);
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/isa.hh Tue Jul 07 09:51:03 2015 +0100
@@ -92,8 +92,8 @@
memset(ipr, 0, sizeof(ipr));
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
int
flattenIntIndex(int reg) const
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/kernel_stats.cc
--- a/src/arch/alpha/kernel_stats.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/kernel_stats.cc Tue Jul 07 09:51:03 2015 +0100
@@ -194,9 +194,9 @@
}
void
-Statistics::serialize(ostream &os)
+Statistics::serialize(CheckpointOut &cp) const
{
- ::Kernel::Statistics::serialize(os);
+ ::Kernel::Statistics::serialize(cp);
int exemode = themode;
SERIALIZE_SCALAR(exemode);
SERIALIZE_SCALAR(idleProcess);
@@ -204,9 +204,9 @@
}
void
-Statistics::unserialize(Checkpoint *cp, const string §ion)
+Statistics::unserialize(CheckpointIn &cp)
{
- ::Kernel::Statistics::unserialize(cp, section);
+ ::Kernel::Statistics::unserialize(cp);
int exemode;
UNSERIALIZE_SCALAR(exemode);
UNSERIALIZE_SCALAR(idleProcess);
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/kernel_stats.hh
--- a/src/arch/alpha/kernel_stats.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/kernel_stats.hh Tue Jul 07 09:51:03 2015 +0100
@@ -86,8 +86,8 @@
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
};
} // namespace Kernel
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/pagetable.cc
--- a/src/arch/alpha/pagetable.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/pagetable.cc Tue Jul 07 09:51:03 2015 +0100
@@ -34,7 +34,7 @@
namespace AlphaISA {
void
-TlbEntry::serialize(std::ostream &os)
+TlbEntry::serialize(CheckpointOut &cp) const
{
SERIALIZE_SCALAR(tag);
SERIALIZE_SCALAR(ppn);
@@ -48,7 +48,7 @@
}
void
-TlbEntry::unserialize(Checkpoint *cp, const std::string §ion)
+TlbEntry::unserialize(CheckpointIn &cp)
{
UNSERIALIZE_SCALAR(tag);
UNSERIALIZE_SCALAR(ppn);
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/pagetable.hh
--- a/src/arch/alpha/pagetable.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/pagetable.hh Tue Jul 07 09:51:03 2015 +0100
@@ -90,7 +90,7 @@
};
// ITB/DTB table entry
-struct TlbEntry
+struct TlbEntry : public Serializable
{
Addr tag; // virtual page number tag
Addr ppn; // physical page number
@@ -124,7 +124,10 @@
}
TlbEntry()
- {}
+ : tag(0), ppn(0), xre(0), xwe(0), asn(0),
+ asma(false), fonr(0), fonw(0), valid(0)
+ {
+ }
void
updateVaddr(Addr new_vaddr)
@@ -139,8 +142,8 @@
return ppn << PageShift;
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
};
} // namespace AlphaISA
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/process.cc Tue Jul 07 09:51:03 2015 +0100
@@ -175,7 +175,7 @@
void
-AlphaLiveProcess::loadState(Checkpoint *cp)
+AlphaLiveProcess::loadState(CheckpointIn &cp)
{
LiveProcess::loadState(cp);
// need to set up ASN after unserialization since M5_pid value may
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/process.hh Tue Jul 07 09:51:03 2015 +0100
@@ -42,7 +42,7 @@
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(Checkpoint *cp);
+ void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void initState();
void argsInit(int intSize, int pageSize);
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/system.cc
--- a/src/arch/alpha/system.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/system.cc Tue Jul 07 09:51:03 2015 +0100
@@ -218,17 +218,17 @@
}
void
-AlphaSystem::serializeSymtab(std::ostream &os)
+AlphaSystem::serializeSymtab(CheckpointOut &cp) const
{
- consoleSymtab->serialize("console_symtab", os);
- palSymtab->serialize("pal_symtab", os);
+ consoleSymtab->serialize("console_symtab", cp);
+ palSymtab->serialize("pal_symtab", cp);
}
void
-AlphaSystem::unserializeSymtab(Checkpoint *cp, const std::string §ion)
+AlphaSystem::unserializeSymtab(CheckpointIn &cp)
{
- consoleSymtab->unserialize("console_symtab", cp, section);
- palSymtab->unserialize("pal_symtab", cp, section);
+ consoleSymtab->unserialize("console_symtab", cp);
+ palSymtab->unserialize("pal_symtab", cp);
}
AlphaSystem *
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/system.hh
--- a/src/arch/alpha/system.hh Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/system.hh Tue Jul 07 09:51:03 2015 +0100
@@ -60,8 +60,8 @@
/**
* Serialization stuff
*/
- virtual void serializeSymtab(std::ostream &os);
- virtual void unserializeSymtab(Checkpoint *cp, const std::string §ion);
+ void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
/** Override startup() to provide a path to call setupFuncEvents()
*/
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Tue Jul 07 09:51:03 2015 +0100
+++ b/src/arch/alpha/tlb.cc Tue Jul 07 09:51:03 2015 +0100
@@ -30,13 +30,15 @@
* Andrew Schultz
*/
+#include "arch/alpha/tlb.hh"
+
+#include <algorithm>
#include <memory>
#include <string>
#include <vector>
#include "arch/alpha/faults.hh"
#include "arch/alpha/pagetable.hh"
-#include "arch/alpha/tlb.hh"
#include "arch/generic/debugfaults.hh"
#include "base/inifile.hh"
#include "base/str.hh"
@@ -62,17 +64,13 @@
#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), nlu(0)
+ : BaseTLB(p), table(p->size), nlu(0)
{
- table = new TlbEntry[size];
- memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
}
TLB::~TLB()
{
- if (table)
- delete [] table;
}
void
@@ -283,7 +281,7 @@
TLB::flushAll()
{
DPRINTF(TLB, "flushAll\n");
- memset(table, 0, sizeof(TlbEntry) * size);
+ std::fill(table.begin(), table.end(), TlbEntry());
flushCache();
lookupTable.clear();
nlu = 0;
@@ -345,25 +343,26 @@
void
-TLB::serialize(ostream &os)
+TLB::serialize(CheckpointOut &cp) const
{
+ const unsigned size(table.size());
SERIALIZE_SCALAR(size);
SERIALIZE_SCALAR(nlu);
- for (int i = 0; i < size; i++) {
- nameOut(os, csprintf("%s.Entry%d", name(), i));
- table[i].serialize(os);
- }
+ for (int i = 0; i < size; i++)
+ table[i].serializeSection(cp, csprintf("Entry%d", i));
}
void
-TLB::unserialize(Checkpoint *cp, const string §ion)
+TLB::unserialize(CheckpointIn &cp)
{
+ unsigned size(0);
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu);
+ table.resize(size);
for (int i = 0; i < size; i++) {
- table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
+ table[i].unserializeSection(cp, csprintf("Entry%d", i));
if (table[i].valid) {
lookupTable.insert(make_pair(table[i].tag, i));
}
diff -r 532f423d6760 -r a6ca6831e775 src/arch/alpha/tlb.hh
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
