changeset 32f3d1c454ec in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=32f3d1c454ec
description:
sim: Make the drain state a global typed enum
The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.
diffstat:
src/arch/arm/table_walker.cc | 6 +-
src/cpu/minor/cpu.cc | 8 ++--
src/cpu/o3/cpu.cc | 12 +++---
src/cpu/o3/cpu.hh | 2 +-
src/dev/arm/flash_device.cc | 4 +-
src/dev/arm/ufs_device.cc | 4 +-
src/dev/copy_engine.cc | 14 ++++----
src/dev/dma_device.cc | 4 +-
src/dev/i8254xGBe.cc | 14 ++++----
src/dev/i8254xGBe.hh | 4 +-
src/dev/ide_disk.cc | 6 +-
src/dev/io_device.cc | 4 +-
src/dev/ns_gige.cc | 8 ++--
src/dev/pcidev.cc | 4 +-
src/dev/sinic.cc | 4 +-
src/mem/cache/base.cc | 4 +-
src/mem/cache/mshr_queue.cc | 6 +-
src/mem/dram_ctrl.cc | 4 +-
src/mem/dramsim2.cc | 4 +-
src/mem/ruby/system/DMASequencer.cc | 4 +-
src/mem/ruby/system/RubyPort.cc | 4 +-
src/mem/ruby/system/Sequencer.cc | 4 +-
src/mem/simple_mem.cc | 4 +-
src/sim/drain.cc | 6 +-
src/sim/drain.hh | 62 ++++++++++++++++++------------------
src/sim/sim_object.cc | 2 +-
src/sim/system.cc | 4 +-
27 files changed, 103 insertions(+), 103 deletions(-)
diffs (truncated from 730 to 300 lines):
diff -r db1b5b20096f -r 32f3d1c454ec src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/arch/arm/table_walker.cc Tue Jul 07 09:51:04 2015 +0100
@@ -139,7 +139,7 @@
{
if (drainManager && stateQueues[L1].empty() && stateQueues[L2].empty() &&
pendingQueue.empty()) {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
drainManager->signalDrainDone();
drainManager = NULL;
@@ -160,13 +160,13 @@
if (state_queues_not_empty || pendingQueue.size()) {
drainManager = dm;
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
DPRINTF(Drain, "TableWalker not drained\n");
// return port drain count plus the table walker itself needs to drain
return 1;
} else {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "TableWalker free, no need to drain\n");
// table walker is drained, but its ports may still need to be drained
diff -r db1b5b20096f -r 32f3d1c454ec src/cpu/minor/cpu.cc
--- a/src/cpu/minor/cpu.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/cpu/minor/cpu.cc Tue Jul 07 09:51:04 2015 +0100
@@ -217,7 +217,7 @@
MinorCPU::signalDrainDone()
{
DPRINTF(Drain, "MinorCPU drain done\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
drainManager->signalDrainDone();
drainManager = NULL;
}
@@ -225,8 +225,8 @@
void
MinorCPU::drainResume()
{
- assert(getDrainState() == Drainable::Drained ||
- getDrainState() == Drainable::Running);
+ assert(getDrainState() == DrainState::Drained ||
+ getDrainState() == DrainState::Running);
if (switchedOut()) {
DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
@@ -243,7 +243,7 @@
wakeup();
pipeline->drainResume();
- setDrainState(Drainable::Running);
+ setDrainState(DrainState::Running);
}
void
diff -r db1b5b20096f -r 32f3d1c454ec src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/cpu/o3/cpu.cc Tue Jul 07 09:51:04 2015 +0100
@@ -539,7 +539,7 @@
{
DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
assert(!switchedOut());
- assert(getDrainState() != Drainable::Drained);
+ assert(getDrainState() != DrainState::Drained);
++numCycles;
ppCycles->notify(1);
@@ -712,7 +712,7 @@
// We don't want to wake the CPU if it is drained. In that case,
// we just want to flag the thread as active and schedule the tick
// event from drainResume() instead.
- if (getDrainState() == Drainable::Drained)
+ if (getDrainState() == DrainState::Drained)
return;
// If we are time 0 or if the last activation time is in the past,
@@ -1004,12 +1004,12 @@
{
// If the CPU isn't doing anything, then return immediately.
if (switchedOut()) {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
DPRINTF(Drain, "Draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
// We only need to signal a drain to the commit stage as this
// initiates squashing controls the draining. Once the commit
@@ -1031,7 +1031,7 @@
return 1;
} else {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "CPU is already drained\n");
if (tickEvent.scheduled())
deschedule(tickEvent);
@@ -1132,7 +1132,7 @@
void
FullO3CPU<Impl>::drainResume()
{
- setDrainState(Drainable::Running);
+ setDrainState(DrainState::Running);
if (switchedOut())
return;
diff -r db1b5b20096f -r 32f3d1c454ec src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/cpu/o3/cpu.hh Tue Jul 07 09:51:04 2015 +0100
@@ -336,7 +336,7 @@
void updateThreadPriority();
/** Is the CPU draining? */
- bool isDraining() const { return getDrainState() == Drainable::Draining; }
+ bool isDraining() const { return getDrainState() == DrainState::Draining; }
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/arm/flash_device.cc
--- a/src/dev/arm/flash_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/arm/flash_device.cc Tue Jul 07 09:51:04 2015 +0100
@@ -601,10 +601,10 @@
if (count) {
DPRINTF(Drain, "Flash device is draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else {
DPRINTF(Drain, "Flash device drained\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
}
return count;
}
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/arm/ufs_device.cc
--- a/src/dev/arm/ufs_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/arm/ufs_device.cc Tue Jul 07 09:51:04 2015 +0100
@@ -2333,10 +2333,10 @@
if (count) {
DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else {
DPRINTF(UFSHostDevice, "UFSDevice drained\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
}
return count;
}
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/copy_engine.cc
--- a/src/dev/copy_engine.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/copy_engine.cc Tue Jul 07 09:51:04 2015 +0100
@@ -140,12 +140,12 @@
cr.status.dma_transfer_status(0);
nextState = DescriptorFetch;
fetchAddress = cr.descChainAddr;
- if (ce->getDrainState() == Drainable::Running)
+ if (ce->getDrainState() == DrainState::Running)
fetchDescriptor(cr.descChainAddr);
} else if (cr.command.append_dma()) {
if (!busy) {
nextState = AddressFetch;
- if (ce->getDrainState() == Drainable::Running)
+ if (ce->getDrainState() == DrainState::Running)
fetchNextAddr(lastDescriptorAddr);
} else
refreshNext = true;
@@ -635,20 +635,20 @@
bool
CopyEngine::CopyEngineChannel::inDrain()
{
- if (ce->getDrainState() == Drainable::Draining) {
+ if (ce->getDrainState() == DrainState::Draining) {
DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
assert(drainManager);
drainManager->signalDrainDone();
drainManager = NULL;
}
- return ce->getDrainState() != Drainable::Running;
+ return ce->getDrainState() != DrainState::Running;
}
unsigned int
CopyEngine::CopyEngineChannel::drain(DrainManager *dm)
{
- if (nextState == Idle || ce->getDrainState() != Drainable::Running)
+ if (nextState == Idle || ce->getDrainState() != DrainState::Running)
return 0;
unsigned int count = 1;
count += cePort.drain(dm);
@@ -667,9 +667,9 @@
count += chan[x]->drain(dm);
if (count)
- setDrainState(Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "CopyEngine not drained\n");
return count;
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/dma_device.cc
--- a/src/dev/dma_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/dma_device.cc Tue Jul 07 09:51:04 2015 +0100
@@ -130,9 +130,9 @@
{
unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm);
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/i8254xGBe.cc Tue Jul 07 09:51:04 2015 +0100
@@ -586,7 +586,7 @@
case REG_RDT:
regs.rdt = val;
DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
- if (getDrainState() == Drainable::Running) {
+ if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
rxDescCache.fetchDescriptors();
} else {
@@ -626,7 +626,7 @@
case REG_TDT:
regs.tdt = val;
DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
- if (getDrainState() == Drainable::Running) {
+ if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
txDescCache.fetchDescriptors();
} else {
@@ -905,7 +905,7 @@
IGbE::DescCache<T>::writeback1()
{
// If we're draining delay issuing this DMA
- if (igbe->getDrainState() != Drainable::Running) {
+ if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
@@ -986,7 +986,7 @@
IGbE::DescCache<T>::fetchDescriptors1()
{
// If we're draining delay issuing this DMA
- if (igbe->getDrainState() != Drainable::Running) {
+ if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
@@ -2051,7 +2051,7 @@
IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
- getDrainState() == Drainable::Running)
+ getDrainState() == DrainState::Running)
schedule(tickEvent, clockEdge(Cycles(1)));
}
@@ -2075,9 +2075,9 @@
if (count) {
DPRINTF(Drain, "IGbE not drained\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff -r db1b5b20096f -r 32f3d1c454ec src/dev/i8254xGBe.hh
--- a/src/dev/i8254xGBe.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/i8254xGBe.hh Tue Jul 07 09:51:04 2015 +0100
@@ -352,7 +352,7 @@
virtual void updateHead(long h) { igbe->regs.rdh(h); }
virtual void enableSm();
virtual void fetchAfterWb() {
- if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
+ if (!igbe->rxTick && igbe->getDrainState() == DrainState::Running)
fetchDescriptors();
}
@@ -414,7 +414,7 @@
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