changeset 80069a602c83 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=80069a602c83
description:
ruby: replace global g_system_ptr with per-object pointers
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single
simulation.
With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.
diffstat:
src/mem/ruby/common/Global.cc | 1 -
src/mem/ruby/common/Global.hh | 3 -
src/mem/ruby/network/MessageBuffer.cc | 2 +-
src/mem/ruby/network/simple/Throttle.cc | 2 +-
src/mem/ruby/profiler/AddressProfiler.cc | 18 +++++-----
src/mem/ruby/profiler/AddressProfiler.hh | 8 +++-
src/mem/ruby/profiler/Profiler.cc | 5 +-
src/mem/ruby/profiler/Profiler.hh | 2 +-
src/mem/ruby/structures/BankedArray.cc | 5 +-
src/mem/ruby/structures/BankedArray.hh | 4 +-
src/mem/ruby/structures/Cache.py | 2 +
src/mem/ruby/structures/CacheMemory.cc | 6 ++-
src/mem/ruby/structures/RubyMemoryControl.cc | 6 ---
src/mem/ruby/structures/WireBuffer.cc | 12 +++---
src/mem/ruby/structures/WireBuffer.hh | 2 +
src/mem/ruby/structures/WireBuffer.py | 2 +
src/mem/ruby/system/DMASequencer.cc | 13 ++++---
src/mem/ruby/system/DMASequencer.hh | 5 +-
src/mem/ruby/system/RubyPort.cc | 46 +++++++++++++++------------
src/mem/ruby/system/RubyPort.hh | 4 +-
src/mem/ruby/system/Sequencer.cc | 9 +++--
src/mem/ruby/system/Sequencer.py | 4 +-
src/mem/ruby/system/System.cc | 10 +----
src/mem/ruby/system/System.hh | 11 +++---
src/mem/slicc/symbols/StateMachine.py | 4 +-
src/mem/slicc/symbols/Type.py | 2 -
26 files changed, 96 insertions(+), 92 deletions(-)
diffs (truncated from 811 to 300 lines):
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/common/Global.cc
--- a/src/mem/ruby/common/Global.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/common/Global.cc Fri Jul 10 16:05:23 2015 -0500
@@ -30,5 +30,4 @@
using namespace std;
-RubySystem* g_system_ptr = 0;
vector<map<uint32_t, AbstractController *> > g_abs_controls;
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/common/Global.hh
--- a/src/mem/ruby/common/Global.hh Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/common/Global.hh Fri Jul 10 16:05:23 2015 -0500
@@ -35,9 +35,6 @@
#include "base/str.hh"
#include "base/types.hh"
-class RubySystem;
-extern RubySystem* g_system_ptr;
-
class AbstractController;
extern std::vector<std::map<uint32_t, AbstractController *> > g_abs_controls;
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/network/MessageBuffer.cc
--- a/src/mem/ruby/network/MessageBuffer.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/network/MessageBuffer.cc Fri Jul 10 16:05:23 2015 -0500
@@ -41,7 +41,7 @@
MessageBuffer::MessageBuffer(const string &name)
: m_time_last_time_size_checked(0), m_time_last_time_enqueue(0),
- m_time_last_time_pop(0), m_last_arrival_time(0)
+ m_time_last_time_pop(0), m_last_arrival_time(0)
{
m_msg_counter = 0;
m_consumer = NULL;
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/network/simple/Throttle.cc
--- a/src/mem/ruby/network/simple/Throttle.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/network/simple/Throttle.cc Fri Jul 10 16:05:23 2015 -0500
@@ -128,7 +128,7 @@
DPRINTF(RubyNetwork, "throttle: %d my bw %d bw spent "
"enqueueing net msg %d time: %lld.\n",
m_node, getLinkBandwidth(), m_units_remaining[vnet],
- g_system_ptr->curCycle());
+ m_ruby_system->curCycle());
// Move the message
in->dequeue();
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/profiler/AddressProfiler.cc
--- a/src/mem/ruby/profiler/AddressProfiler.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/profiler/AddressProfiler.cc Fri Jul 10 16:05:23 2015 -0500
@@ -32,7 +32,6 @@
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/profiler/AddressProfiler.hh"
#include "mem/ruby/profiler/Profiler.hh"
-#include "mem/ruby/system/System.hh"
using namespace std;
typedef AddressProfiler::AddressMap AddressMap;
@@ -64,7 +63,7 @@
void
printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
- string description)
+ string description, Profiler *profiler)
{
const int records_printed = 100;
@@ -82,7 +81,7 @@
out << "Total_entries_" << description << ": " << record_map.size()
<< endl;
- if (g_system_ptr->getProfiler()->getAllInstructions())
+ if (profiler->getAllInstructions())
out << "Total_Instructions_" << description << ": " << misses << endl;
else
out << "Total_data_misses_" << description << ": " << misses << endl;
@@ -143,7 +142,8 @@
<< endl;
}
-AddressProfiler::AddressProfiler(int num_of_sequencers)
+AddressProfiler::AddressProfiler(int num_of_sequencers, Profiler *profiler)
+ : m_profiler(profiler)
{
m_num_of_sequencers = num_of_sequencers;
clearStats();
@@ -183,20 +183,20 @@
out << "---------------" << endl;
out << endl;
printSorted(out, m_num_of_sequencers, m_dataAccessTrace,
- "block_address");
+ "block_address", m_profiler);
out << endl;
out << "Hot MacroData Blocks" << endl;
out << "--------------------" << endl;
out << endl;
printSorted(out, m_num_of_sequencers, m_macroBlockAccessTrace,
- "macroblock_address");
+ "macroblock_address", m_profiler);
out << "Hot Instructions" << endl;
out << "----------------" << endl;
out << endl;
printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
- "pc_address");
+ "pc_address", m_profiler);
}
if (m_all_instructions) {
@@ -205,7 +205,7 @@
out << "-------------------------" << endl;
out << endl;
printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
- "pc_address");
+ "pc_address", m_profiler);
out << endl;
}
@@ -222,7 +222,7 @@
out << endl;
printSorted(out, m_num_of_sequencers, m_retryProfileMap,
- "block_address");
+ "block_address", m_profiler);
out << endl;
}
}
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/profiler/AddressProfiler.hh
--- a/src/mem/ruby/profiler/AddressProfiler.hh Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/profiler/AddressProfiler.hh Fri Jul 10 16:05:23 2015 -0500
@@ -35,9 +35,9 @@
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/profiler/AccessTraceForAddress.hh"
+#include "mem/ruby/profiler/Profiler.hh"
class Set;
@@ -47,7 +47,7 @@
typedef m5::hash_map<Address, AccessTraceForAddress> AddressMap;
public:
- AddressProfiler(int num_of_sequencers);
+ AddressProfiler(int num_of_sequencers, Profiler *profiler);
~AddressProfiler();
void printStats(std::ostream& out) const;
@@ -87,6 +87,8 @@
Histogram m_getx_sharing_histogram;
Histogram m_gets_sharing_histogram;
+ Profiler *m_profiler;
+
//added by SS
bool m_hot_lines;
bool m_all_instructions;
@@ -100,7 +102,7 @@
void printSorted(std::ostream& out, int num_of_sequencers,
const AddressProfiler::AddressMap &record_map,
- std::string description);
+ std::string description, Profiler *profiler);
inline std::ostream&
operator<<(std::ostream& out, const AddressProfiler& obj)
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/profiler/Profiler.cc
--- a/src/mem/ruby/profiler/Profiler.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/profiler/Profiler.cc Fri Jul 10 16:05:23 2015 -0500
@@ -56,7 +56,6 @@
#include "mem/ruby/profiler/AddressProfiler.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/system/Sequencer.hh"
-#include "mem/ruby/system/System.hh"
using namespace std;
using m5::stl_helpers::operator<<;
@@ -66,12 +65,12 @@
m_hot_lines = p->hot_lines;
m_all_instructions = p->all_instructions;
- m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers);
+ m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
m_address_profiler_ptr->setHotLines(m_hot_lines);
m_address_profiler_ptr->setAllInstructions(m_all_instructions);
if (m_all_instructions) {
- m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers);
+ m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
m_inst_profiler_ptr->setHotLines(m_hot_lines);
m_inst_profiler_ptr->setAllInstructions(m_all_instructions);
}
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/profiler/Profiler.hh
--- a/src/mem/ruby/profiler/Profiler.hh Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/profiler/Profiler.hh Fri Jul 10 16:05:23 2015 -0500
@@ -66,7 +66,7 @@
class Profiler
{
public:
- Profiler(const RubySystemParams *);
+ Profiler(const RubySystemParams *params);
~Profiler();
void wakeup();
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/structures/BankedArray.cc
--- a/src/mem/ruby/structures/BankedArray.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/structures/BankedArray.cc Fri Jul 10 16:05:23 2015 -0500
@@ -34,7 +34,8 @@
#include "mem/ruby/system/System.hh"
BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
- unsigned int startIndexBit)
+ unsigned int startIndexBit, RubySystem *rs)
+ : m_ruby_system(rs)
{
this->banks = banks;
this->accessLatency = accessLatency;
@@ -70,7 +71,7 @@
busyBanks[bank].idx = idx;
busyBanks[bank].startAccess = curTick();
busyBanks[bank].endAccess = curTick() +
- (accessLatency-1) * g_system_ptr->clockPeriod();
+ (accessLatency-1) * m_ruby_system->clockPeriod();
return true;
}
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/structures/BankedArray.hh
--- a/src/mem/ruby/structures/BankedArray.hh Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/structures/BankedArray.hh Fri Jul 10 16:05:23 2015 -0500
@@ -35,6 +35,7 @@
#include <vector>
#include "mem/ruby/common/TypeDefines.hh"
+#include "mem/ruby/system/System.hh"
#include "sim/core.hh"
class BankedArray
@@ -44,6 +45,7 @@
Cycles accessLatency;
unsigned int bankBits;
unsigned int startIndexBit;
+ RubySystem *m_ruby_system;
class AccessRecord
{
@@ -62,7 +64,7 @@
public:
BankedArray(unsigned int banks, Cycles accessLatency,
- unsigned int startIndexBit);
+ unsigned int startIndexBit, RubySystem *rs);
// Note: We try the access based on the cache index, not the address
// This is so we don't get aliasing on blocks being replaced
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/structures/Cache.py
--- a/src/mem/ruby/structures/Cache.py Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/structures/Cache.py Fri Jul 10 16:05:23 2015 -0500
@@ -28,6 +28,7 @@
# Brad Beckmann
from m5.params import *
+from m5.proxy import *
from m5.SimObject import SimObject
class RubyCache(SimObject):
@@ -46,3 +47,4 @@
dataAccessLatency = Param.Cycles(1, "cycles for a data array access")
tagAccessLatency = Param.Cycles(1, "cycles for a tag array access")
resourceStalls = Param.Bool(False, "stall if there is a resource failure")
+ ruby_system = Param.RubySystem(Parent.any, "")
diff -r dd3ab1f109ad -r 80069a602c83 src/mem/ruby/structures/CacheMemory.cc
--- a/src/mem/ruby/structures/CacheMemory.cc Fri Jul 10 16:05:23 2015 -0500
+++ b/src/mem/ruby/structures/CacheMemory.cc Fri Jul 10 16:05:23 2015 -0500
@@ -53,8 +53,10 @@
CacheMemory::CacheMemory(const Params *p)
: SimObject(p),
- dataArray(p->dataArrayBanks, p->dataAccessLatency, p->start_index_bit),
- tagArray(p->tagArrayBanks, p->tagAccessLatency, p->start_index_bit)
+ dataArray(p->dataArrayBanks, p->dataAccessLatency,
+ p->start_index_bit, p->ruby_system),
+ tagArray(p->tagArrayBanks, p->tagAccessLatency,
+ p->start_index_bit, p->ruby_system)
{
m_cache_size = p->size;
m_latency = p->latency;
diff -r dd3ab1f109ad -r 80069a602c83
src/mem/ruby/structures/RubyMemoryControl.cc
--- a/src/mem/ruby/structures/RubyMemoryControl.cc Fri Jul 10 16:05:23
2015 -0500
+++ b/src/mem/ruby/structures/RubyMemoryControl.cc Fri Jul 10 16:05:23
2015 -0500
@@ -310,12 +310,6 @@
physical_address_t addr = memRef->m_addr;
int bank = getBank(addr);
- DPRINTF(RubyMemory,
- "New memory request%7d: %#08x %c arrived at %10d bank = %3x sched
%c\n",
- m_msg_counter, addr, memRef->m_is_mem_read ? 'R':'W',
- memRef->m_time * g_system_ptr->clockPeriod(),
- bank, m_event.scheduled() ? 'Y':'N');
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