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This might be a silly question but I was wondering: Some of the protocols have getCacheEntry without a way to pass whether to setMRU or not; they default to false. What is the reason for these automatically being false? Since the sequencer cannot set the recently used status, how do these caches update their entry information? - Brandon Potter On July 19, 2015, 11:45 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2957/ > ----------------------------------------------------------- > > (Updated July 19, 2015, 11:45 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10937:3724230bfee5 > --------------------------- > ruby: call setMRU from L1 controllers, not from sequencer > Currently the sequencer calls the function setMRU that updates the replacement > policy structures with the first level caches. While functionally this is > correct, the problem is that this requires calling findTagInSet() which is an > expensive function. This patch removes the calls to setMRU from the > sequencer. > All controllers should now update the replacement policy on their own. > > The set and the way index for a given cache entry can be found within the > AbstractCacheEntry structure. Use these indicies to update the replacement > policy structures. > > > Diffs > ----- > > src/mem/ruby/system/Sequencer.cc 3a925f9856b1 > src/mem/protocol/MOESI_hammer-cache.sm 3a925f9856b1 > src/mem/protocol/RubySlicc_Types.sm 3a925f9856b1 > src/mem/ruby/structures/CacheMemory.hh 3a925f9856b1 > src/mem/ruby/structures/CacheMemory.cc 3a925f9856b1 > src/mem/protocol/MESI_Three_Level-L0cache.sm 3a925f9856b1 > src/mem/protocol/MESI_Two_Level-L1cache.sm 3a925f9856b1 > src/mem/protocol/MI_example-cache.sm 3a925f9856b1 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm 3a925f9856b1 > src/mem/protocol/MOESI_CMP_token-L1cache.sm 3a925f9856b1 > > Diff: http://reviews.gem5.org/r/2957/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
