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Review request for Default. Repository: gem5 Description ------- Trying to run an SE system with varying threads per core (SMT cores + Non-SMT cores) caused failures due to the CPU id assignment logic. The comment about thread assignment (worrying about core 0 not having tid 0) seems not to be valid given that our configuration scripts initialize them in order. This removes that constraint so a heterogenously threaded sytem can work. Diffs ----- src/cpu/base.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/sim/System.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/sim/system.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/sim/system.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 Diff: http://reviews.gem5.org/r/2994/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
