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Review request for Default. Repository: gem5 Description ------- For the ARM ISA, certain variables are only updated when a necessary change is detected. Having 2 SMT threads share a TLB resulted in these not being updated as required. This patch adds a thread context identifer to assist in the invalidation of these variables. Diffs ----- src/arch/arm/tlb.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 src/arch/arm/tlb.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 Diff: http://reviews.gem5.org/r/3000/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
