changeset 4820cc8408b0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4820cc8408b0
description:
ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on
each
individual cache block to be invalidated via requests from the mandatory
queue.
diffstat:
src/mem/protocol/RubySlicc_Types.sm | 5 +++++
src/mem/ruby/structures/CacheMemory.cc | 24 ++++++++++++++++++++++++
src/mem/ruby/structures/CacheMemory.hh | 5 +++++
3 files changed, 34 insertions(+), 0 deletions(-)
diffs (82 lines):
diff -r 53d63eeee46f -r 4820cc8408b0 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/RubySlicc_Types.sm Mon Jul 20 09:15:18 2015 -0500
@@ -1,5 +1,6 @@
/*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -155,6 +156,10 @@
void recordRequestType(CacheRequestType);
bool checkResourceAvailable(CacheResourceType, Address);
+ int getCacheSize();
+ int getNumBlocks();
+ Address getAddressAtIdx(int);
+
Scalar demand_misses;
Scalar demand_hits;
}
diff -r 53d63eeee46f -r 4820cc8408b0 src/mem/ruby/structures/CacheMemory.cc
--- a/src/mem/ruby/structures/CacheMemory.cc Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/ruby/structures/CacheMemory.cc Mon Jul 20 09:15:18 2015 -0500
@@ -1,5 +1,6 @@
/*
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -134,6 +135,29 @@
return -1; // Not found
}
+// Given an unique cache block identifier (idx): return the valid address
+// stored by the cache block. If the block is invalid/notpresent, the
+// function returns the 0 address
+Address
+CacheMemory::getAddressAtIdx(int idx) const
+{
+ Address tmp(0);
+
+ int set = idx / m_cache_assoc;
+ assert(set < m_cache_num_sets);
+
+ int way = idx - set * m_cache_assoc;
+ assert (way < m_cache_assoc);
+
+ AbstractCacheEntry* entry = m_cache[set][way];
+ if (entry == NULL ||
+ entry->m_Permission == AccessPermission_Invalid ||
+ entry->m_Permission == AccessPermission_NotPresent) {
+ return tmp;
+ }
+ return entry->m_Address;
+}
+
bool
CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr)
diff -r 53d63eeee46f -r 4820cc8408b0 src/mem/ruby/structures/CacheMemory.hh
--- a/src/mem/ruby/structures/CacheMemory.hh Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/ruby/structures/CacheMemory.hh Mon Jul 20 09:15:18 2015 -0500
@@ -1,5 +1,6 @@
/*
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -131,6 +132,10 @@
Stats::Scalar numTagArrayStalls;
Stats::Scalar numDataArrayStalls;
+ int getCacheSize() const { return m_cache_size; }
+ int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
+ Address getAddressAtIdx(int idx) const;
+
private:
// convert a Address to its location in the cache
int64 addressToCacheSet(const Address& address) const;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
