changeset 7de6f95a0817 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7de6f95a0817
description:
ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify
each
cache block's access permission. This information can be useful when
making
replacement decisions.
diffstat:
src/mem/ruby/structures/AbstractReplacementPolicy.hh | 5 +++++
src/mem/ruby/structures/CacheMemory.cc | 13 +++++++++++++
src/mem/ruby/structures/CacheMemory.hh | 2 ++
3 files changed, 20 insertions(+), 0 deletions(-)
diffs (61 lines):
diff -r 3c11859e4a81 -r 7de6f95a0817
src/mem/ruby/structures/AbstractReplacementPolicy.hh
--- a/src/mem/ruby/structures/AbstractReplacementPolicy.hh Mon Jul 20
09:15:18 2015 -0500
+++ b/src/mem/ruby/structures/AbstractReplacementPolicy.hh Mon Jul 20
09:15:18 2015 -0500
@@ -34,6 +34,8 @@
#include "params/ReplacementPolicy.hh"
#include "sim/sim_object.hh"
+class CacheMemory;
+
class AbstractReplacementPolicy : public SimObject
{
public:
@@ -52,6 +54,9 @@
virtual bool useOccupancy() const { return false; }
+ void setCache(CacheMemory * pCache) {m_cache = pCache;}
+ CacheMemory * m_cache;
+
protected:
unsigned m_num_sets; /** total number of sets */
unsigned m_assoc; /** set associativity */
diff -r 3c11859e4a81 -r 7de6f95a0817 src/mem/ruby/structures/CacheMemory.cc
--- a/src/mem/ruby/structures/CacheMemory.cc Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/ruby/structures/CacheMemory.cc Mon Jul 20 09:15:18 2015 -0500
@@ -63,6 +63,7 @@
m_latency = p->latency;
m_cache_assoc = p->assoc;
m_replacementPolicy_ptr = p->replacement_policy;
+ m_replacementPolicy_ptr->setCache(this);
m_start_index_bit = p->start_index_bit;
m_is_instruction_only_cache = p->is_icache;
m_resource_stalls = p->resourceStalls;
@@ -592,3 +593,15 @@
return true;
}
}
+
+bool
+CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
+{
+ return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
+}
+
+bool
+CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
+{
+ return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
+}
diff -r 3c11859e4a81 -r 7de6f95a0817 src/mem/ruby/structures/CacheMemory.hh
--- a/src/mem/ruby/structures/CacheMemory.hh Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/ruby/structures/CacheMemory.hh Mon Jul 20 09:15:18 2015 -0500
@@ -100,6 +100,8 @@
Cycles getTagLatency() const { return tagArray.getLatency(); }
Cycles getDataLatency() const { return dataArray.getLatency(); }
+ bool isBlockInvalid(int64 cache_set, int64 loc);
+ bool isBlockNotBusy(int64 cache_set, int64 loc);
// Hook for checkpointing the contents of the cache
void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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